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author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-08-21 17:33:42 +0000 |
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committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-08-21 17:33:42 +0000 |
commit | 5578ceab945bd2181d220ab17462c26014f29cae (patch) | |
tree | b6d20795d60dc4f33c3361ea578951e2bc75f922 /target-sparc/translate.c | |
parent | 1a7de94aa40729b4d7ed8f37c642304866232f40 (diff) | |
download | hqemu-5578ceab945bd2181d220ab17462c26014f29cae.zip hqemu-5578ceab945bd2181d220ab17462c26014f29cae.tar.gz |
Use initial CPU definition structure for some CPU fields instead of copying
them around, based on patch by Luis Pureza.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5042 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/translate.c')
-rw-r--r-- | target-sparc/translate.c | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 6315218..3f15fb9 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -59,7 +59,7 @@ typedef struct DisasContext { int fpu_enabled; int address_mask_32bit; struct TranslationBlock *tb; - uint32_t features; + sparc_def_t *def; } DisasContext; // This function uses non-native bit order @@ -1905,10 +1905,10 @@ static inline TCGv get_src2(unsigned int insn, TCGv def) } #define CHECK_IU_FEATURE(dc, FEATURE) \ - if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \ + if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; #define CHECK_FPU_FEATURE(dc, FEATURE) \ - if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \ + if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto nfpu_insn; /* before an instruction, dc->pc must be static */ @@ -4141,7 +4141,7 @@ static void disas_sparc_insn(DisasContext * dc) goto jmp_insn; #endif case 0x3b: /* flush */ - if (!((dc)->features & CPU_FEATURE_FLUSH)) + if (!((dc)->def->features & CPU_FEATURE_FLUSH)) goto unimp_flush; tcg_gen_helper_0_1(helper_flush, cpu_dst); break; @@ -4742,13 +4742,10 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, last_pc = dc->pc; dc->npc = (target_ulong) tb->cs_base; dc->mem_idx = cpu_mmu_index(env); - dc->features = env->features; - if ((dc->features & CPU_FEATURE_FLOAT)) { + dc->def = env->def; + if ((dc->def->features & CPU_FEATURE_FLOAT)) dc->fpu_enabled = cpu_fpu_enabled(env); -#if defined(CONFIG_USER_ONLY) - dc->features |= CPU_FEATURE_FLOAT128; -#endif - } else + else dc->fpu_enabled = 0; #ifdef TARGET_SPARC64 dc->address_mask_32bit = env->pstate & PS_AM; |