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| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-25 18:50:28 +0000 |
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| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-25 18:50:28 +0000 |
| commit | 20c9f095c4536e64e60432a5c72fce38e8306cbb (patch) | |
| tree | fe68375301d78efc0eb73138da36199a00bcde7a /target-sparc/cpu.h | |
| parent | 8d05ea8a33c9d450d2a3079e967c69ea38ec28ba (diff) | |
| download | hqemu-20c9f095c4536e64e60432a5c72fce38e8306cbb.zip hqemu-20c9f095c4536e64e60432a5c72fce38e8306cbb.tar.gz | |
Implement Sparc64 CPU timers using ptimers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2860 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/cpu.h')
| -rw-r--r-- | target-sparc/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index b067d7b..c5ccd28 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -226,10 +226,12 @@ typedef struct CPUSPARCState { uint64_t mgregs[8]; /* mmu general registers */ uint64_t fprs; uint64_t tick_cmpr, stick_cmpr; + void *tick, *stick; uint64_t gsr; uint32_t gl; // UA2005 /* UA 2005 hyperprivileged registers */ uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr; + void *hstick; // UA 2005 #endif #if !defined(TARGET_SPARC64) && !defined(reg_T2) target_ulong t2; @@ -292,6 +294,9 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); void raise_exception(int tt); void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, int is_asi); +void do_tick_set_count(void *opaque, uint64_t count); +uint64_t do_tick_get_count(void *opaque); +void do_tick_set_limit(void *opaque, uint64_t limit); #include "cpu-all.h" |
