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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2007-05-27 19:36:00 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2007-05-27 19:36:00 +0000
commit1b2e93c175a947653326efce9a6f36791d458691 (patch)
tree0a64de498eae9e09102ed8ec3ed812de5ea18064 /target-sparc/cpu.h
parentb3a2319792ad5c0f0f8c3d2f4d02b95fd7efbc69 (diff)
downloadhqemu-1b2e93c175a947653326efce9a6f36791d458691.zip
hqemu-1b2e93c175a947653326efce9a6f36791d458691.tar.gz
Separate fault for code access to unassigned memory
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2876 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/cpu.h')
-rw-r--r--target-sparc/cpu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index c5ccd28..2158629 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -40,6 +40,7 @@
#define TT_DFAULT 0x09
#define TT_TOVF 0x0a
#define TT_EXTINT 0x10
+#define TT_CODE_ACCESS 0x21
#define TT_DATA_ACCESS 0x29
#define TT_DIV_ZERO 0x2a
#define TT_NCP_INSN 0x24
@@ -47,6 +48,7 @@
#else
#define TT_TFAULT 0x08
#define TT_TMISS 0x09
+#define TT_CODE_ACCESS 0x0a
#define TT_ILL_INSN 0x10
#define TT_PRIV_INSN 0x11
#define TT_NFPU_INSN 0x20
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