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authorAurelien Jarno <aurelien@aurel32.net>2015-05-25 01:28:56 +0200
committerAurelien Jarno <aurelien@aurel32.net>2015-06-12 12:02:48 +0200
commit1d565b21e1aecbb0da6589f3c4ea83c9c788ad63 (patch)
tree91f484f105e06f76fe8b62ad159ee91a2c18c780 /target-sh4/cpu.h
parent60eb27fe4951fbe6cf5e24cc3d6df7e97c43a909 (diff)
downloadhqemu-1d565b21e1aecbb0da6589f3c4ea83c9c788ad63.zip
hqemu-1d565b21e1aecbb0da6589f3c4ea83c9c788ad63.tar.gz
target-sh4: split out Q and M from of SR and optimize div1
Splitting Q and M out of SR, it's possible to optimize div1 by using TCG code instead of an helper. At the same time removed the now unused gen_copy_bit_i32 function. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-sh4/cpu.h')
-rw-r--r--target-sh4/cpu.h12
1 files changed, 9 insertions, 3 deletions
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index a308c53..4a027a6 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -139,6 +139,8 @@ typedef struct CPUSH4State {
uint32_t gregs[24]; /* general registers */
float32 fregs[32]; /* floating point registers */
uint32_t sr; /* status register (with T split out) */
+ uint32_t sr_m; /* M bit of status register */
+ uint32_t sr_q; /* Q bit of status register */
uint32_t sr_t; /* T bit of status register */
uint32_t ssr; /* saved status register */
uint32_t spc; /* saved program counter */
@@ -334,13 +336,17 @@ static inline int cpu_ptel_pr (uint32_t ptel)
static inline target_ulong cpu_read_sr(CPUSH4State *env)
{
- return env->sr | (env->sr_t << SR_T);
+ return env->sr | (env->sr_m << SR_M) |
+ (env->sr_q << SR_Q) |
+ (env->sr_t << SR_T);
}
static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
{
- env->sr_t = sr & (1u << SR_T);
- env->sr = sr & ~(1u << SR_T);
+ env->sr_m = (sr >> SR_M) & 1;
+ env->sr_q = (sr >> SR_Q) & 1;
+ env->sr_t = (sr >> SR_T) & 1;
+ env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
}
static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
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