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authorAurelien Jarno <aurelien@aurel32.net>2015-06-13 00:46:03 +0200
committerAlexander Graf <agraf@suse.de>2015-06-17 12:40:52 +0200
commit3da0ab35292fe93640cfdd95aa8bedec8f145d2c (patch)
treeb1002d1195a3401c89ffa0ce1b7242baa8d83904 /target-s390x/cpu.c
parent83bb161299c019e25a3add59504f0b69e6257dcd (diff)
downloadhqemu-3da0ab35292fe93640cfdd95aa8bedec8f145d2c.zip
hqemu-3da0ab35292fe93640cfdd95aa8bedec8f145d2c.tar.gz
target-s390x: PER: add Breaking-Event-Address register
This patch adds support for PER Breaking-Event-Address register. Like real hardware, it save the current PSW address when the PSW address is changed by an instruction. We have to take care of optimizations QEMU does, a branch to the next instruction is still a branch. This register is copied to low core memory when a program exception happens. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-s390x/cpu.c')
-rw-r--r--target-s390x/cpu.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 4daf643..69bac35 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -117,6 +117,9 @@ static void s390_cpu_initial_reset(CPUState *s)
env->cregs[0] = CR0_RESET;
env->cregs[14] = CR14_RESET;
+ /* architectured initial value for Breaking-Event-Address register */
+ env->gbea = 1;
+
env->pfault_token = -1UL;
env->ext_index = -1;
for (i = 0; i < ARRAY_SIZE(env->io_index); i++) {
@@ -152,6 +155,9 @@ static void s390_cpu_full_reset(CPUState *s)
env->cregs[0] = CR0_RESET;
env->cregs[14] = CR14_RESET;
+ /* architectured initial value for Breaking-Event-Address register */
+ env->gbea = 1;
+
env->pfault_token = -1UL;
env->ext_index = -1;
for (i = 0; i < ARRAY_SIZE(env->io_index); i++) {
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