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authorAlexander Graf <agraf@suse.de>2012-01-21 03:48:58 +0100
committerAlexander Graf <agraf@suse.de>2012-02-02 02:47:45 +0100
commitdcb2b9e1003a9179650b44c747faa4e5767ce92b (patch)
treee9a610a04a2b25f627d773e1137f68ffee9b0320 /target-ppc
parent53319166318f365db3bb72cf5a80618211ecf9df (diff)
downloadhqemu-dcb2b9e1003a9179650b44c747faa4e5767ce92b.zip
hqemu-dcb2b9e1003a9179650b44c747faa4e5767ce92b.tar.gz
PPC: rename msync to msync_4xx
The msync instruction as defined today is only valid on 4xx cores, not on e500 which also supports msync, but treats it the same way as sync. Rename it to reflect that it's 4xx only. Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
-rw-r--r--target-ppc/translate.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 18d52a9..adde65b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6172,7 +6172,7 @@ static void gen_mbar(DisasContext *ctx)
}
/* msync replaces sync on 440 */
-static void gen_msync(DisasContext *ctx)
+static void gen_msync_4xx(DisasContext *ctx)
{
/* interpreted as no-op */
}
@@ -8579,7 +8579,7 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
PPC_BOOKE, PPC2_BOOKE206),
-GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
+GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
PPC_BOOKE, PPC2_BOOKE206),
GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
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