diff options
author | Alexander Graf <agraf@suse.de> | 2012-06-20 21:20:29 +0200 |
---|---|---|
committer | Alexander Graf <agraf@suse.de> | 2012-06-24 01:04:51 +0200 |
commit | e42a61f185f859246c14445b6e98e195eb3b977b (patch) | |
tree | 1e3ee47605c54b3986af5816dead928211b6f209 /target-ppc/translate.c | |
parent | 84755ed51e6266b115322834933ce404a2fbf3f9 (diff) | |
download | hqemu-e42a61f185f859246c14445b6e98e195eb3b977b.zip hqemu-e42a61f185f859246c14445b6e98e195eb3b977b.tar.gz |
PPC: Add support for MSR_CM
The BookE variant of MSR_SF is MSR_CM. Implement everything it takes in TCG to
support running 64bit code with MSR_CM set.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/translate.c')
-rw-r--r-- | target-ppc/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 9103fd5..73ee74b 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9626,7 +9626,7 @@ static inline void gen_intermediate_code_internal(CPUPPCState *env, ctx.access_type = -1; ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; #if defined(TARGET_PPC64) - ctx.sf_mode = msr_sf; + ctx.sf_mode = msr_is_64bit(env, env->msr); ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); #endif ctx.fpu_enabled = msr_fp; |