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author | Paolo Bonzini <pbonzini@redhat.com> | 2015-11-13 13:34:23 +0100 |
---|---|---|
committer | Timothy Pearson <tpearson@raptorengineering.com> | 2019-11-29 19:28:20 -0600 |
commit | 1668ef39ca2ea4fc3cd32a62ee650049796967be (patch) | |
tree | 3143e1cdb6ee0dbe0f4bc290c7820f5332f072a0 /target-ppc/translate.c | |
parent | 32eab01bec17c35f2cad0daeaf874c4ebb3aac70 (diff) | |
download | hqemu-1668ef39ca2ea4fc3cd32a62ee650049796967be.zip hqemu-1668ef39ca2ea4fc3cd32a62ee650049796967be.tar.gz |
ppc: cleanup logging
Avoid "naked" qemu_log, bring documentation for DEBUG #defines
up to date.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target-ppc/translate.c')
-rw-r--r-- | target-ppc/translate.c | 22 |
1 files changed, 9 insertions, 13 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 9e1371e..bfbc63e 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11543,12 +11543,10 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) } /* Is opcode *REALLY* valid ? */ if (unlikely(handler->handler == &gen_invalid)) { - if (qemu_log_enabled()) { - qemu_log("invalid/unsupported opcode: " - "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", - opc1(ctx.opcode), opc2(ctx.opcode), - opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); - } + qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " + "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", + opc1(ctx.opcode), opc2(ctx.opcode), + opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); } else { uint32_t inval; @@ -11559,13 +11557,11 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) } if (unlikely((ctx.opcode & inval) != 0)) { - if (qemu_log_enabled()) { - qemu_log("invalid bits: %08x for opcode: " - "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", - ctx.opcode & inval, opc1(ctx.opcode), - opc2(ctx.opcode), opc3(ctx.opcode), - ctx.opcode, ctx.nip - 4); - } + qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " + "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", + ctx.opcode & inval, opc1(ctx.opcode), + opc2(ctx.opcode), opc3(ctx.opcode), + ctx.opcode, ctx.nip - 4); gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); break; } |