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| author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2015-01-26 19:51:58 +0530 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2015-03-09 14:59:53 +0100 |
| commit | ad3e67d05a65da2e3696ed45b999e061ccb7a879 (patch) | |
| tree | 80685f08307ace44bafe3ffc88ad3be4b2218cb3 /target-ppc/mmu-hash64.h | |
| parent | ee9a569ab88edd0755402aaf31ec0c69decf7756 (diff) | |
| download | hqemu-ad3e67d05a65da2e3696ed45b999e061ccb7a879.zip hqemu-ad3e67d05a65da2e3696ed45b999e061ccb7a879.tar.gz | |
target-ppc: Use right page size with hash table lookup
We look at two sizes specified in ISA (4K, 64K). If not found matching,
we consider it 16MB.
Without this patch we would fail to lookup address above 16MB range.
Below 16MB happened to work before because the kernel have a liner
mapping and we always looked up hash for 0xc000000000000000. The
actual real address was computed by using the 16MB offset
with the real address found with the above hash.
Without Fix:
(gdb) x/16x 0xc000000001000000
0xc000000001000000 <list_entries+453208>: Cannot access memory at address 0xc000000001000000
(gdb)
With Fix:
(gdb) x/16x 0xc000000001000000
0xc000000001000000 <list_entries+453208>: 0x00000000 0x00000000 0x00000000 0x00000000
0xc000000001000010 <list_entries+453224>: 0x00000000 0x00000000 0x00000000 0x00000000
0xc000000001000020 <list_entries+453240>: 0x00000000 0x00000000 0x00000000 0x00000000
0xc000000001000030 <list_entries+453256>: 0x00000000 0x00000000 0x00000000 0x00000000
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/mmu-hash64.h')
| -rw-r--r-- | target-ppc/mmu-hash64.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h index 49e385d..291750f 100644 --- a/target-ppc/mmu-hash64.h +++ b/target-ppc/mmu-hash64.h @@ -37,6 +37,9 @@ void ppc_hash64_store_hpte(CPUPPCState *env, target_ulong index, #define SLB_VSID_C 0x0000000000000080ULL /* class */ #define SLB_VSID_LP 0x0000000000000030ULL #define SLB_VSID_ATTR 0x0000000000000FFFULL +#define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP) +#define SLB_VSID_4K 0x0000000000000000ULL +#define SLB_VSID_64K 0x0000000000000110ULL /* * Hash page table definitions |
