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| author | David Gibson <david@gibson.dropbear.id.au> | 2016-01-15 17:54:42 +1100 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineering.com> | 2019-11-29 19:30:22 -0600 |
| commit | 8e89404f07fa6c51b3270ea4f6f941cb215064fa (patch) | |
| tree | 5bbddd458f9a15dc9c1639fee1aa9636364993af /target-ppc/mmu-hash64.h | |
| parent | 326e218f1df27874c6cb924531bf616143be224b (diff) | |
| download | hqemu-8e89404f07fa6c51b3270ea4f6f941cb215064fa.zip hqemu-8e89404f07fa6c51b3270ea4f6f941cb215064fa.tar.gz | |
target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG
Now that the TCG and spapr code has been extended to allow (semi-)
arbitrary page encodings in the CPU's 'sps' table, we can add the many
page sizes supported by real POWER7 and POWER8 hardware that we previously
didn't support in TCG.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/mmu-hash64.h')
| -rw-r--r-- | target-ppc/mmu-hash64.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h index 34cf975..ab0f86b 100644 --- a/target-ppc/mmu-hash64.h +++ b/target-ppc/mmu-hash64.h @@ -48,6 +48,8 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, #define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP) #define SLB_VSID_4K 0x0000000000000000ULL #define SLB_VSID_64K 0x0000000000000110ULL +#define SLB_VSID_16M 0x0000000000000100ULL +#define SLB_VSID_16G 0x0000000000000120ULL /* * Hash page table definitions |
