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| author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-21 13:08:23 +0000 |
|---|---|---|
| committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-21 13:08:23 +0000 |
| commit | bd928ebafe5a5e318d5ec71c1aec4400721179ae (patch) | |
| tree | 69f122c3528aee2444efdcb46d35d5edb36141ee /target-ppc/cpu.h | |
| parent | 325e651fb78cc970e170aa502bae6e3fa2c26db7 (diff) | |
| download | hqemu-bd928ebafe5a5e318d5ec71c1aec4400721179ae.zip hqemu-bd928ebafe5a5e318d5ec71c1aec4400721179ae.tar.gz | |
Fix PowerPC 7xx definitions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3713 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 7cbc8da..365d836 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -357,6 +357,7 @@ union ppc_tlb_t { /*****************************************************************************/ /* Machine state register bits definition */ #define MSR_SF 63 /* Sixty-four-bit mode hflags */ +#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */ #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ #define MSR_SHV 60 /* hypervisor state hflags */ #define MSR_CM 31 /* Computation mode for BookE hflags */ @@ -1115,16 +1116,29 @@ static inline int cpu_mmu_index (CPUState *env) #define SPR_440_CCR1 (0x378) #define SPR_DCRIPR (0x37B) #define SPR_PPR (0x380) +#define SPR_750_GQR0 (0x390) #define SPR_440_DNV0 (0x390) +#define SPR_750_GQR1 (0x391) #define SPR_440_DNV1 (0x391) +#define SPR_750_GQR2 (0x392) #define SPR_440_DNV2 (0x392) +#define SPR_750_GQR3 (0x393) #define SPR_440_DNV3 (0x393) +#define SPR_750_GQR4 (0x394) #define SPR_440_DTV0 (0x394) +#define SPR_750_GQR5 (0x395) #define SPR_440_DTV1 (0x395) +#define SPR_750_GQR6 (0x396) #define SPR_440_DTV2 (0x396) +#define SPR_750_GQR7 (0x397) #define SPR_440_DTV3 (0x397) +#define SPR_750_THRM4 (0x398) +#define SPR_750CL_HID2 (0x398) #define SPR_440_DVLIM (0x398) +#define SPR_750_WPAR (0x399) #define SPR_440_IVLIM (0x399) +#define SPR_750_DMAU (0x39A) +#define SPR_750_DMAL (0x39B) #define SPR_440_RSTCFG (0x39B) #define SPR_BOOKE_DCDBTRL (0x39C) #define SPR_BOOKE_DCDBTRH (0x39D) @@ -1231,9 +1245,11 @@ static inline int cpu_mmu_index (CPUState *env) #define SPR_Exxx_L1CSR0 (0x3F2) #define SPR_ICTRL (0x3F3) #define SPR_HID2 (0x3F3) +#define SPR_750CL_HID4 (0x3F3) #define SPR_Exxx_L1CSR1 (0x3F3) #define SPR_440_DBDR (0x3F3) #define SPR_LDSTDB (0x3F4) +#define SPR_750_TDCL (0x3F4) #define SPR_40x_IAC1 (0x3F4) #define SPR_MMUCSR0 (0x3F4) #define SPR_DABR (0x3F5) @@ -1250,12 +1266,13 @@ static inline int cpu_mmu_index (CPUState *env) #define SPR_MMUCFG (0x3F7) #define SPR_LDSTCR (0x3F8) #define SPR_L2PMCR (0x3F8) -#define SPR_750_HID2 (0x3F8) +#define SPR_750FX_HID2 (0x3F8) #define SPR_620_BUSCSR (0x3F8) #define SPR_Exxx_L1FINV0 (0x3F8) #define SPR_L2CR (0x3F9) #define SPR_620_L2CR (0x3F9) #define SPR_L3CR (0x3FA) +#define SPR_750_TDCH (0x3FA) #define SPR_IABR2 (0x3FA) #define SPR_40x_DCCR (0x3FA) #define SPR_620_L2SR (0x3FA) |
