diff options
author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-04 05:26:09 +0000 |
---|---|---|
committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-04 05:26:09 +0000 |
commit | bd7d9a6d7bed629cf8363cf8283f1d88946faddd (patch) | |
tree | e21a7da28b21bc86936ecb216c3a1ed3078ba38d /target-ppc/cpu.h | |
parent | f78fb44e825421d386bc44090907d159a04839ef (diff) | |
download | hqemu-bd7d9a6d7bed629cf8363cf8283f1d88946faddd.zip hqemu-bd7d9a6d7bed629cf8363cf8283f1d88946faddd.tar.gz |
ppc: cleanup register types
- use target_ulong for gpr and dyngen registers
- remove ppc_gpr_t type
- define 64-bit dyngen registers for GPE register on 32-bit targets
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/cpu.h')
-rw-r--r-- | target-ppc/cpu.h | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index c7291ed..0de7653 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -27,13 +27,11 @@ #if defined (TARGET_PPC64) /* PowerPC 64 definitions */ -typedef uint64_t ppc_gpr_t; #define TARGET_LONG_BITS 64 #define TARGET_PAGE_BITS 12 #else /* defined (TARGET_PPC64) */ /* PowerPC 32 definitions */ -typedef uint32_t ppc_gpr_t; #define TARGET_LONG_BITS 32 #if defined(TARGET_PPCEMB) @@ -531,19 +529,22 @@ struct CPUPPCState { /* First are the most commonly used resources * during translated code execution */ -#if (TARGET_LONG_BITS > HOST_LONG_BITS) || !defined(TARGET_PPC64) +#if TARGET_LONG_BITS > HOST_LONG_BITS + target_ulong t0, t1, t2; +#endif +#if !defined(TARGET_PPC64) /* temporary fixed-point registers - * used to emulate 64 bits registers on 32 bits hosts + * used to emulate 64 bits registers on 32 bits targets */ - uint64_t t0, t1, t2; + uint64_t t0_64, t1_64, t2_64; #endif ppc_avr_t avr0, avr1, avr2; /* general purpose registers */ - ppc_gpr_t gpr[32]; + target_ulong gpr[32]; #if !defined(TARGET_PPC64) /* Storage for GPR MSB, used by the SPE extension */ - ppc_gpr_t gprh[32]; + target_ulong gprh[32]; #endif /* LR */ target_ulong lr; @@ -561,7 +562,7 @@ struct CPUPPCState { /* machine state register */ target_ulong msr; /* temporary general purpose registers */ - ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */ + target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */ /* Floating point execution context */ /* temporary float registers */ @@ -614,7 +615,7 @@ struct CPUPPCState { ppc_avr_t avr[32]; uint32_t vscr; /* SPE registers */ - ppc_gpr_t spe_acc; + target_ulong spe_acc; float_status spe_status; uint32_t spe_fscr; |