diff options
author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-24 02:03:55 +0000 |
---|---|---|
committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-24 02:03:55 +0000 |
commit | 6b542af760f44409b40441225fbef31a3b4bdbe1 (patch) | |
tree | d7371ec9d77673e4d2cb59a249750fe0cc0d0529 /target-ppc/cpu.h | |
parent | 69facb7897ef6404175b4739751f9255fc0c8a2e (diff) | |
download | hqemu-6b542af760f44409b40441225fbef31a3b4bdbe1.zip hqemu-6b542af760f44409b40441225fbef31a3b4bdbe1.tar.gz |
Fix incorrect debug prints (reported by Paul Brook).
Remove obsolete / duplicated debug prints and improve output consistency.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3725 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/cpu.h')
-rw-r--r-- | target-ppc/cpu.h | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 365d836..e780764 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -30,7 +30,6 @@ typedef uint64_t ppc_gpr_t; #define TARGET_GPR_BITS 64 #define TARGET_LONG_BITS 64 -#define REGX "%016" PRIx64 #define TARGET_PAGE_BITS 12 #else /* defined (TARGET_PPC64) */ @@ -43,11 +42,9 @@ typedef uint64_t ppc_gpr_t; */ typedef uint64_t ppc_gpr_t; #define TARGET_GPR_BITS 64 -#define REGX "%08" PRIx64 #else /* (HOST_LONG_BITS >= 64) */ typedef uint32_t ppc_gpr_t; #define TARGET_GPR_BITS 32 -#define REGX "%08" PRIx32 #endif /* (HOST_LONG_BITS >= 64) */ #define TARGET_LONG_BITS 32 @@ -74,6 +71,7 @@ typedef uint32_t ppc_gpr_t; #include "cpu-defs.h" +#define REGX "%016" PRIx64 #define ADDRX TARGET_FMT_lx #define PADDRX TARGET_FMT_plx @@ -792,6 +790,24 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid); #endif #endif +static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn) +{ + uint64_t gprv; + + gprv = env->gpr[gprn]; +#if !defined(TARGET_PPC64) + if (env->flags & POWERPC_FLAG_SPE) { + /* If the CPU implements the SPE extension, we have to get the + * high bits of the GPR from the gprh storage area + */ + gprv &= 0xFFFFFFFFULL; + gprv |= (uint64_t)env->gprh[gprn] << 32; + } +#endif + + return gprv; +} + /* Device control registers */ int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp); int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); |