Fix for 32-bit MIPS.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4622 c046a42c-6fe2-441c-8c8c-71466251a162

1 files changed, 10 insertions, 9 deletions

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8290220..3ff7aec 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1904,15 +1904,16 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
             {
                 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
                 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
-
-                tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
-                tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
-                tcg_gen_div_i64(r_tmp1, cpu_T[0], cpu_T[1]);
-                tcg_gen_rem_i64(r_tmp2, cpu_T[0], cpu_T[1]);
-                tcg_gen_ext32s_tl(r_tmp1, r_tmp1);
-                tcg_gen_ext32s_tl(r_tmp2, r_tmp2);
-                gen_store_LO(r_tmp1, 0);
-                gen_store_HI(r_tmp2, 0);
+                TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
+
+                tcg_gen_ext_tl_i64(r_tmp1, cpu_T[0]);
+                tcg_gen_ext_tl_i64(r_tmp2, cpu_T[1]);
+                tcg_gen_div_i64(r_tmp3, r_tmp1, r_tmp2);
+                tcg_gen_rem_i64(r_tmp2, r_tmp1, r_tmp2);
+                tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp3);
+                tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp2);
+                gen_store_LO(cpu_T[0], 0);
+                gen_store_HI(cpu_T[1], 0);
             }
             gen_set_label(l1);
         }