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author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-09-25 16:53:15 +0000 |
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committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-09-25 16:53:15 +0000 |
commit | 42532189dfba7a5675225b7b3d6da3d80f8c2447 (patch) | |
tree | 3d1e8f329f076ccb5717e0962370cf9d22fef118 /target-mips | |
parent | b51eaa8218f4bd9cfd9a10b7014676035289ef56 (diff) | |
download | hqemu-42532189dfba7a5675225b7b3d6da3d80f8c2447.zip hqemu-42532189dfba7a5675225b7b3d6da3d80f8c2447.tar.gz |
Timer start/stop implementation, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3237 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
-rw-r--r-- | target-mips/exec.h | 2 | ||||
-rw-r--r-- | target-mips/op.c | 13 | ||||
-rw-r--r-- | target-mips/op_helper.c | 10 |
3 files changed, 22 insertions, 3 deletions
diff --git a/target-mips/exec.h b/target-mips/exec.h index 5b8577e..d5aaded 100644 --- a/target-mips/exec.h +++ b/target-mips/exec.h @@ -153,6 +153,8 @@ uint32_t cpu_mips_get_random (CPUState *env); uint32_t cpu_mips_get_count (CPUState *env); void cpu_mips_store_count (CPUState *env, uint32_t value); void cpu_mips_store_compare (CPUState *env, uint32_t value); +void cpu_mips_start_count(CPUState *env); +void cpu_mips_stop_count(CPUState *env); void cpu_mips_update_irq (CPUState *env); void cpu_mips_clock_init (CPUState *env); void cpu_mips_tlb_flush (CPUState *env, int flush_global); diff --git a/target-mips/op.c b/target-mips/op.c index b353644..b8c5ce8 100644 --- a/target-mips/op.c +++ b/target-mips/op.c @@ -1886,9 +1886,8 @@ void op_mttc0_status(void) void op_mtc0_intctl (void) { - /* vectored interrupts not implemented, timer on int 7, - no performance counters. */ - env->CP0_IntCtl |= T0 & 0x000002e0; + /* vectored interrupts not implemented, no performance counters. */ + env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0); RETURN(); } @@ -1908,12 +1907,20 @@ void op_mtc0_srsmap (void) void op_mtc0_cause (void) { uint32_t mask = 0x00C00300; + uint32_t old = env->CP0_Cause; if (env->insn_flags & ISA_MIPS32R2) mask |= 1 << CP0Ca_DC; env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask); + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) + CALL_FROM_TB1(cpu_mips_stop_count, env); + else + CALL_FROM_TB1(cpu_mips_start_count, env); + } + /* Handle the software interrupt as an hardware one, as they are very similar */ if (T0 & CP0Ca_IP_mask) { diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 6405f80..6b007a6 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -265,6 +265,16 @@ void cpu_mips_store_compare(CPUState *env, uint32_t value) cpu_abort(env, "mtc0 compare\n"); } +void cpu_mips_start_count(CPUState *env) +{ + cpu_abort(env, "start count\n"); +} + +void cpu_mips_stop_count(CPUState *env) +{ + cpu_abort(env, "stop count\n"); +} + void cpu_mips_update_irq(CPUState *env) { cpu_abort(env, "mtc0 status / mtc0 cause\n"); |