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| author | Yongbok Kim <yongbok.kim@imgtec.com> | 2015-06-30 15:44:28 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2015-07-15 14:07:17 +0100 |
| commit | d4f4f0d5d9e74c19614479592c8bc865d92773d0 (patch) | |
| tree | 5c11026b1c413633ef2c4ce567ba274089d322ec /target-mips/msa_helper.c | |
| parent | 4dc89b782095d7a0b919fafd7b1322b3cb1279f1 (diff) | |
| download | hqemu-d4f4f0d5d9e74c19614479592c8bc865d92773d0.zip hqemu-d4f4f0d5d9e74c19614479592c8bc865d92773d0.tar.gz | |
target-mips: fix to clear MSACSR.Cause
MSACSR.Cause bits are needed to be cleared before a vector floating-point
instructions.
FEXDO.df, FEXUPL.df and FEXUPR.df were missed out.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/msa_helper.c')
| -rw-r--r-- | target-mips/msa_helper.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target-mips/msa_helper.c b/target-mips/msa_helper.c index 26ffdc7..a1cb48f 100644 --- a/target-mips/msa_helper.c +++ b/target-mips/msa_helper.c @@ -2642,6 +2642,8 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwt = &(env->active_fpu.fpr[wt].wr); uint32_t i; + clear_msacsr_cause(env); + switch (df) { case DF_WORD: for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { @@ -3192,6 +3194,8 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pws = &(env->active_fpu.fpr[ws].wr); uint32_t i; + clear_msacsr_cause(env); + switch (df) { case DF_WORD: for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { @@ -3224,6 +3228,8 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pws = &(env->active_fpu.fpr[ws].wr); uint32_t i; + clear_msacsr_cause(env); + switch (df) { case DF_WORD: for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
