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author | Edgar E. Iglesias <edgar@axis.com> | 2010-08-06 12:21:16 +0200 |
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committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2010-08-06 12:21:16 +0200 |
commit | 138afb024bbd115553a344e06d93011a283d1316 (patch) | |
tree | ebd809dcf604b85e3099678522c1e43890c4394b /target-mips/cpu.h | |
parent | d087bb3e38fbb705ae65c55457b9ef3e0a5d2511 (diff) | |
download | hqemu-138afb024bbd115553a344e06d93011a283d1316.zip hqemu-138afb024bbd115553a344e06d93011a283d1316.tar.gz |
mips: Add support for VInt and VEIC irq modes
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
Diffstat (limited to 'target-mips/cpu.h')
-rw-r--r-- | target-mips/cpu.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index b8e6fee..19511d7 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -525,6 +525,29 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) env->active_tc.gpr[2] = 0; } +static inline int cpu_mips_hw_interrupts_pending(CPUState *env) +{ + int32_t pending; + int32_t status; + int r; + + pending = env->CP0_Cause & CP0Ca_IP_mask; + status = env->CP0_Status & CP0Ca_IP_mask; + + if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { + /* A MIPS configured with a vectorizing external interrupt controller + will feed a vector into the Cause pending lines. The core treats + the status lines as a vector level, not as indiviual masks. */ + r = pending > status; + } else { + /* A MIPS configured with compatibility or VInt (Vectored Interrupts) + treats the pending lines as individual interrupt lines, the status + lines are individual masks. */ + r = pending & status; + } + return r; +} + #include "cpu-all.h" /* Memory access type : |