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| author | Leon Alrae <leon.alrae@imgtec.com> | 2014-07-07 11:24:00 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-11-03 11:48:34 +0000 |
| commit | 9456c2fbcd82dd82328ac6e7602a815582b1043e (patch) | |
| tree | 7a2f9f2763b0945ec990ae22f3847476f89c5de5 /target-mips/cpu.h | |
| parent | 92ceb440d47b9ef3ba860cdc75a7e31563a7dc0c (diff) | |
| download | hqemu-9456c2fbcd82dd82328ac6e7602a815582b1043e.zip hqemu-9456c2fbcd82dd82328ac6e7602a815582b1043e.tar.gz | |
target-mips: add TLBINV support
For Standard TLB configuration (Config.MT=1):
TLBINV invalidates a set of TLB entries based on ASID. The virtual address is
ignored in the entry match. TLB entries which have their G bit set to 1 are not
modified.
TLBINVF causes all entries to be invalidated.
Single TLB entry can be marked as invalid on TLB entry write by having
EntryHi.EHINV set to 1.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index a9e1bc2..9c38b4f 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -34,6 +34,7 @@ struct r4k_tlb_t { uint_fast16_t XI1:1; uint_fast16_t RI0:1; uint_fast16_t RI1:1; + uint_fast16_t EHINV:1; target_ulong PFN[2]; }; @@ -47,6 +48,8 @@ struct CPUMIPSTLBContext { void (*helper_tlbwr)(struct CPUMIPSState *env); void (*helper_tlbp)(struct CPUMIPSState *env); void (*helper_tlbr)(struct CPUMIPSState *env); + void (*helper_tlbinv)(struct CPUMIPSState *env); + void (*helper_tlbinvf)(struct CPUMIPSState *env); union { struct { r4k_tlb_t tlb[MIPS_TLB_MAX]; @@ -282,6 +285,7 @@ struct CPUMIPSState { target_ulong CP0_BadVAddr; int32_t CP0_Count; target_ulong CP0_EntryHi; +#define CP0EnHi_EHINV 10 int32_t CP0_Compare; int32_t CP0_Status; #define CP0St_CU3 31 @@ -393,6 +397,7 @@ struct CPUMIPSState { uint32_t CP0_Config4; uint32_t CP0_Config4_rw_bitmask; #define CP0C4_M 31 +#define CP0C4_IE 29 #define CP0C4_KScrExist 16 uint32_t CP0_Config5; uint32_t CP0_Config5_rw_bitmask; @@ -529,6 +534,8 @@ void r4k_helper_tlbwi(CPUMIPSState *env); void r4k_helper_tlbwr(CPUMIPSState *env); void r4k_helper_tlbp(CPUMIPSState *env); void r4k_helper_tlbr(CPUMIPSState *env); +void r4k_helper_tlbinv(CPUMIPSState *env); +void r4k_helper_tlbinvf(CPUMIPSState *env); void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write, bool is_exec, int unused, |
