diff options
author | Andreas Färber <afaerber@suse.de> | 2013-06-29 04:18:45 +0200 |
---|---|---|
committer | Andreas Färber <afaerber@suse.de> | 2013-07-27 00:04:17 +0200 |
commit | 5b50e790f9e9403d11b4164193b76530ee85a2a1 (patch) | |
tree | 63244f49c1b53b05d1d8ddc795643e376dd55971 /target-i386 | |
parent | 986a2998932e978e63fc3b7ead1fef81f7aad52e (diff) | |
download | hqemu-5b50e790f9e9403d11b4164193b76530ee85a2a1.zip hqemu-5b50e790f9e9403d11b4164193b76530ee85a2a1.tar.gz |
cpu: Introduce CPUClass::gdb_{read,write}_register()
Completes migration of target-specific code to new target-*/gdbstub.c.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-i386')
-rw-r--r-- | target-i386/Makefile.objs | 1 | ||||
-rw-r--r-- | target-i386/cpu-qom.h | 3 | ||||
-rw-r--r-- | target-i386/cpu.c | 2 | ||||
-rw-r--r-- | target-i386/gdbstub.c | 27 |
4 files changed, 24 insertions, 9 deletions
diff --git a/target-i386/Makefile.objs b/target-i386/Makefile.objs index c1d4f05..3b629d4d 100644 --- a/target-i386/Makefile.objs +++ b/target-i386/Makefile.objs @@ -1,6 +1,7 @@ obj-y += translate.o helper.o cpu.o obj-y += excp_helper.o fpu_helper.o cc_helper.o int_helper.o svm_helper.o obj-y += smm_helper.o misc_helper.o mem_helper.o seg_helper.o +obj-y += gdbstub.o obj-$(CONFIG_SOFTMMU) += machine.o arch_memory_mapping.o arch_dump.o obj-$(CONFIG_KVM) += kvm.o hyperv.o obj-$(CONFIG_NO_KVM) += kvm-stub.o diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h index d928562..60d2b5d 100644 --- a/target-i386/cpu-qom.h +++ b/target-i386/cpu-qom.h @@ -106,4 +106,7 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); + #endif diff --git a/target-i386/cpu.c b/target-i386/cpu.c index df9832e..2b59b7d 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2538,6 +2538,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->dump_state = x86_cpu_dump_state; cc->set_pc = x86_cpu_set_pc; cc->synchronize_from_tb = x86_cpu_synchronize_from_tb; + cc->gdb_read_register = x86_cpu_gdb_read_register; + cc->gdb_write_register = x86_cpu_gdb_write_register; cc->get_arch_id = x86_cpu_get_arch_id; cc->get_paging_enabled = x86_cpu_get_paging_enabled; #ifndef CONFIG_USER_ONLY diff --git a/target-i386/gdbstub.c b/target-i386/gdbstub.c index 0a4d97d..15bebef 100644 --- a/target-i386/gdbstub.c +++ b/target-i386/gdbstub.c @@ -17,6 +17,9 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see <http://www.gnu.org/licenses/>. */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" #ifdef TARGET_X86_64 static const int gpr_map[16] = { @@ -35,8 +38,11 @@ static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; #define IDX_XMM_REGS (IDX_FP_REGS + 16) #define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS) -static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n) +int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) { + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + if (n < CPU_NB_REGS) { if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]); @@ -108,8 +114,9 @@ static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n) return 0; } -static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf) +static int x86_cpu_gdb_load_seg(X86CPU *cpu, int sreg, uint8_t *mem_buf) { + CPUX86State *env = &cpu->env; uint16_t selector = ldl_p(mem_buf); if (selector != env->segs[sreg].selector) { @@ -135,8 +142,10 @@ static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf) return 4; } -static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n) +int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; uint32_t tmp; if (n < CPU_NB_REGS) { @@ -179,17 +188,17 @@ static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n) return 4; case IDX_SEG_REGS: - return cpu_x86_gdb_load_seg(env, R_CS, mem_buf); + return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf); case IDX_SEG_REGS + 1: - return cpu_x86_gdb_load_seg(env, R_SS, mem_buf); + return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf); case IDX_SEG_REGS + 2: - return cpu_x86_gdb_load_seg(env, R_DS, mem_buf); + return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf); case IDX_SEG_REGS + 3: - return cpu_x86_gdb_load_seg(env, R_ES, mem_buf); + return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf); case IDX_SEG_REGS + 4: - return cpu_x86_gdb_load_seg(env, R_FS, mem_buf); + return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf); case IDX_SEG_REGS + 5: - return cpu_x86_gdb_load_seg(env, R_GS, mem_buf); + return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf); case IDX_FP_REGS + 8: env->fpuc = ldl_p(mem_buf); |