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author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-22 12:36:31 +0000 |
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committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-22 12:36:31 +0000 |
commit | c1c379686f01821a2cae04f35abe4068e6796359 (patch) | |
tree | 651c399c18339557941e4cda2b98f15a0fd5fde6 /target-i386/translate.c | |
parent | 12e26b75d49adbd69ce5f00659f5c51d19d45304 (diff) | |
download | hqemu-c1c379686f01821a2cae04f35abe4068e6796359.zip hqemu-c1c379686f01821a2cae04f35abe4068e6796359.tar.gz |
optimization of shifts by a constant
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4524 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386/translate.c')
-rw-r--r-- | target-i386/translate.c | 72 |
1 files changed, 68 insertions, 4 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c index 04db898..844cdb2 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -1432,7 +1432,6 @@ static void gen_inc(DisasContext *s1, int ot, int d, int c) tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); } -/* XXX: add faster immediate case */ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, int is_right, int is_arith) { @@ -1493,6 +1492,57 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ } +static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, + int is_right, int is_arith) +{ + int mask; + + if (ot == OT_QUAD) + mask = 0x3f; + else + mask = 0x1f; + + /* load */ + if (op1 == OR_TMP0) + gen_op_ld_T0_A0(ot + s->mem_index); + else + gen_op_mov_TN_reg(ot, 0, op1); + + op2 &= mask; + if (op2 != 0) { + if (is_right) { + if (is_arith) { + gen_exts(ot, cpu_T[0]); + tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], op2 - 1); + tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2); + } else { + gen_extu(ot, cpu_T[0]); + tcg_gen_shri_tl(cpu_tmp0, cpu_T[0], op2 - 1); + tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2); + } + } else { + tcg_gen_shli_tl(cpu_tmp0, cpu_T[0], op2 - 1); + tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2); + } + } + + /* store */ + if (op1 == OR_TMP0) + gen_op_st_T0_A0(ot + s->mem_index); + else + gen_op_mov_reg_T0(ot, op1); + + /* update eflags if non zero shift */ + if (op2 != 0) { + tcg_gen_mov_tl(cpu_cc_src, cpu_tmp0); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + if (is_right) + s->cc_op = CC_OP_SARB + ot; + else + s->cc_op = CC_OP_SHLB + ot; + } +} + static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) { if (arg2 >= 0) @@ -1770,9 +1820,23 @@ static void gen_shift(DisasContext *s1, int op, int ot, int d, int s) static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c) { - /* currently not optimized */ - gen_op_movl_T1_im(c); - gen_shift(s1, op, ot, d, OR_TMP1); + switch(op) { + case OP_SHL: + case OP_SHL1: + gen_shift_rm_im(s1, ot, d, c, 0, 0); + break; + case OP_SHR: + gen_shift_rm_im(s1, ot, d, c, 1, 0); + break; + case OP_SAR: + gen_shift_rm_im(s1, ot, d, c, 1, 1); + break; + default: + /* currently not optimized */ + gen_op_movl_T1_im(c); + gen_shift(s1, op, ot, d, OR_TMP1); + break; + } } static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr) |