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| author | Huang Ying <ying.huang@intel.com> | 2009-06-23 10:05:14 +0800 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2009-07-09 16:04:53 -0500 |
| commit | 79c4f6b08009a1d23177c2be8bd003253cf3686a (patch) | |
| tree | c9a9e72451d20ba2ae8e0f5a14301522281add70 /target-i386/cpu.h | |
| parent | 2152390dca9975b1aaaa6f0518ebdd359477905b (diff) | |
| download | hqemu-79c4f6b08009a1d23177c2be8bd003253cf3686a.zip hqemu-79c4f6b08009a1d23177c2be8bd003253cf3686a.tar.gz | |
QEMU: MCE: Add MCE simulation to qemu/tcg
- MCE features are initialized when VCPU is intialized according to CPUID.
- A monitor command "mce" is added to inject a MCE.
- A new interrupt mask: CPU_INTERRUPT_MCE is added to inject the MCE.
aliguori: fix build for linux-user
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'target-i386/cpu.h')
| -rw-r--r-- | target-i386/cpu.h | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 4a8608e..6f7478a 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -204,6 +204,7 @@ #define CR4_DE_MASK (1 << 3) #define CR4_PSE_MASK (1 << 4) #define CR4_PAE_MASK (1 << 5) +#define CR4_MCE_MASK (1 << 6) #define CR4_PGE_MASK (1 << 7) #define CR4_PCE_MASK (1 << 8) #define CR4_OSFXSR_SHIFT 9 @@ -250,6 +251,17 @@ #define PG_ERROR_RSVD_MASK 0x08 #define PG_ERROR_I_D_MASK 0x10 +#define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */ + +#define MCE_CAP_DEF MCG_CTL_P +#define MCE_BANKS_DEF 10 + +#define MCG_STATUS_MCIP (1UL<<2) /* machine check in progress */ + +#define MCI_STATUS_VAL (1UL<<63) /* valid error */ +#define MCI_STATUS_OVER (1UL<<62) /* previous errors lost */ +#define MCI_STATUS_UC (1UL<<61) /* uncorrected error */ + #define MSR_IA32_TSC 0x10 #define MSR_IA32_APICBASE 0x1b #define MSR_IA32_APICBASE_BSP (1<<8) @@ -290,6 +302,11 @@ #define MSR_MTRRdefType 0x2ff +#define MSR_MC0_CTL 0x400 +#define MSR_MC0_STATUS 0x401 +#define MSR_MC0_ADDR 0x402 +#define MSR_MC0_MISC 0x403 + #define MSR_EFER 0xc0000080 #define MSR_EFER_SCE (1 << 0) @@ -678,6 +695,11 @@ typedef struct CPUX86State { /* in order to simplify APIC support, we leave this pointer to the user */ struct APICState *apic_state; + + uint64 mcg_cap; + uint64 mcg_status; + uint64 mcg_ctl; + uint64 *mce_banks; } CPUX86State; CPUX86State *cpu_x86_init(const char *cpu_model); @@ -842,7 +864,7 @@ static inline int cpu_get_time_fast(void) #define cpu_signal_handler cpu_x86_signal_handler #define cpu_list x86_cpu_list -#define CPU_SAVE_VERSION 9 +#define CPU_SAVE_VERSION 10 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel |
