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author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-06-04 17:39:33 +0000 |
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committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-06-04 17:39:33 +0000 |
commit | 33c263df7f87ca0cd170a6017a668205488ab010 (patch) | |
tree | 27b748ccdc0758a9af86122d1e054357ace0b2fa /target-i386/cpu.h | |
parent | 4f57689a8d5db61fb42434ed70142b2b0751da68 (diff) | |
download | hqemu-33c263df7f87ca0cd170a6017a668205488ab010.zip hqemu-33c263df7f87ca0cd170a6017a668205488ab010.tar.gz |
SVM: added tsc_offset
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4668 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386/cpu.h')
-rw-r--r-- | target-i386/cpu.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 9f60738..18cb6ad 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -119,9 +119,9 @@ #define ID_MASK 0x00200000 /* hidden flags - used internally by qemu to represent additional cpu - states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid - using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring - with eflags. */ + states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not + redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit + position to ease oring with eflags. */ /* current cpl */ #define HF_CPL_SHIFT 0 /* true if soft mmu is being used */ @@ -543,6 +543,7 @@ typedef struct CPUX86State { target_phys_addr_t vm_hsave; target_phys_addr_t vm_vmcb; + uint64_t tsc_offset; uint64_t intercept; uint16_t intercept_cr_read; uint16_t intercept_cr_write; |