Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140513' into staging

target-arm queue:
 * update libvixl to 1.4
 * remove version_minimum_id_old from ARM devices
 * stellaris_enet tx/rx/migration overhaul
 * various minor fixes for coverity issues

# gpg: Signature made Tue 13 May 2014 16:25:12 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20140513:
  hw/arm/omap_gpmc: Avoid buffer overrun filling prefetch FIFO
  hw/arm/stellaris: Correct handling of GPTM TAR register
  hw/timer/exynos4210_mct: Avoid overflow in exynos4210_ltick_recalc_count
  hw/dma/omap_dma: Add (uint32_t) casts when shifting uint16_t by 16
  hw/arm/omap1: Avoid unintended sign extension writing omap_rtc YEARS_REG
  hw/net/cadence_gem: Remove dead code
  hw/intc/allwinner-a10-pic: Add missing 'break'
  target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchanged
  hw/net/stellaris_enet: Convert to vmstate
  hw/net/stellaris_enet: Get rid of rx_fifo pointer
  hw/net/stellaris_enet: Fix debug format strings
  hw/net/stellaris_enet: Correctly implement the TR and THR registers
  hw/net/stellaris_enet: Rewrite tx fifo handling code
  hw/net/stellaris_enet: Correct handling of packet padding
  hw/net/stellaris_enet: Restructure tx_fifo code to avoid buffer overrun
  savevm: Remove all the unneeded version_minimum_id_old (arm)
  disas/libvixl: Update to libvixl 1.4

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2 files changed, 7 insertions, 5 deletions

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3be917c..417161e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2081,6 +2081,13 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     ARMCPU *cpu = arm_env_get_cpu(env);
 
+    if (env->cp15.c1_sys == value) {
+        /* Skip the TLB flush if nothing actually changed; Linux likes
+         * to do a lot of pointless SCTLR writes.
+         */
+        return;
+    }
+
     env->cp15.c1_sys = value;
     /* ??? Lots of these bits are not implemented.  */
     /* This may enable/disable the MMU, so do a TLB flush.  */
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 810ba27..5092dcd 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -39,7 +39,6 @@ static const VMStateDescription vmstate_vfp = {
     .name = "cpu/vfp",
     .version_id = 3,
     .minimum_version_id = 3,
-    .minimum_version_id_old = 3,
     .fields = (VMStateField[]) {
         VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
         /* The xregs array is a little awkward because element 1 (FPSCR)
@@ -72,7 +71,6 @@ static const VMStateDescription vmstate_iwmmxt = {
     .name = "cpu/iwmmxt",
     .version_id = 1,
     .minimum_version_id = 1,
-    .minimum_version_id_old = 1,
     .fields = (VMStateField[]) {
         VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
         VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
@@ -92,7 +90,6 @@ static const VMStateDescription vmstate_m = {
     .name = "cpu/m",
     .version_id = 1,
     .minimum_version_id = 1,
-    .minimum_version_id_old = 1,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
         VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
@@ -116,7 +113,6 @@ static const VMStateDescription vmstate_thumb2ee = {
     .name = "cpu/thumb2ee",
     .version_id = 1,
     .minimum_version_id = 1,
-    .minimum_version_id_old = 1,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(env.teecr, ARMCPU),
         VMSTATE_UINT32(env.teehbr, ARMCPU),
@@ -224,7 +220,6 @@ const VMStateDescription vmstate_arm_cpu = {
     .name = "cpu",
     .version_id = 17,
     .minimum_version_id = 17,
-    .minimum_version_id_old = 17,
     .pre_save = cpu_pre_save,
     .post_load = cpu_post_load,
     .fields = (VMStateField[]) {