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author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-06-03 17:44:37 +0000 |
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committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-06-03 17:44:37 +0000 |
commit | bfed01fc79cb2da1c6ca700bb0ce9238ce2974c7 (patch) | |
tree | 4260b2f4481ff9250eaacf143273a8c21796c5bf /target-arm | |
parent | 08ab123c2dba80cf6b7f0df563af14a7d902f759 (diff) | |
download | hqemu-bfed01fc79cb2da1c6ca700bb0ce9238ce2974c7.zip hqemu-bfed01fc79cb2da1c6ca700bb0ce9238ce2974c7.tar.gz |
Clean up of some target specifics in exec.c/cpu-exec.c.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2936 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm')
-rw-r--r-- | target-arm/exec.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/target-arm/exec.h b/target-arm/exec.h index d99dfa5..b25c7e2 100644 --- a/target-arm/exec.h +++ b/target-arm/exec.h @@ -48,6 +48,20 @@ static inline void regs_to_env(void) int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int is_user, int is_softmmu); +static inline int cpu_halted(CPUState *env) { + if (!env->halted) + return 0; + /* An interrupt wakes the CPU even if the I and F CPSR bits are + set. We use EXITTB to silently wake CPU without causing an + actual interrupt. */ + if (env->interrupt_request & + (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)) { + env->halted = 0; + return 0; + } + return EXCP_HALTED; +} + #if !defined(CONFIG_USER_ONLY) #include "softmmu_exec.h" #endif |