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author | Peter Maydell <peter.maydell@linaro.org> | 2014-09-29 18:48:48 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2014-09-29 18:48:48 +0100 |
commit | c0f4af171999eda4e49de5169906ce98246457f0 (patch) | |
tree | f49424c8ec77adc33a948e299259c8f30966cd66 /target-arm/translate.h | |
parent | f59492b984934170f624487ffdec983a0102ba96 (diff) | |
download | hqemu-c0f4af171999eda4e49de5169906ce98246457f0.zip hqemu-c0f4af171999eda4e49de5169906ce98246457f0.tar.gz |
target-arm: Don't handle c15_cpar changes via tb_flush()
At the moment we try to handle c15_cpar with the strategy of:
* emit generated code which makes assumptions about its value
* when the register value changes call tb_flush() to throw
away the now-invalid generated code
This works because XScale CPUs are always uniprocessor, but
it's confusing because it suggests that the same approach can
be taken for other registers. It also means we do a tb_flush()
on CPU reset, which makes multithreaded linux-user binaries
even more likely to fail than would otherwise be the case.
Replace it with a combination of TB flags for the access
checks done on cp0/cp1 for the XScale and iwMMXt instructions,
plus a runtime check for cp2..cp13 coprocessor accesses.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1411056959-23070-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/translate.h')
-rw-r--r-- | target-arm/translate.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-arm/translate.h b/target-arm/translate.h index b90d275..85c6f9d 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -52,6 +52,8 @@ typedef struct DisasContext { bool is_ldex; /* True if a single-step exception will be taken to the current EL */ bool ss_same_el; + /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ + int c15_cpar; #define TMP_A64_MAX 16 int tmp_a64_count; TCGv_i64 tmp_a64[TMP_A64_MAX]; |