summaryrefslogtreecommitdiffstats
path: root/target-arm/translate.c
diff options
context:
space:
mode:
authorpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-03-31 03:45:13 +0000
committerpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-03-31 03:45:13 +0000
commitf51bbbfefe73120a85a8d24a029d37c9c0f3a001 (patch)
treeded0d23ca903c3c124ceba5ccf342521d6f98c22 /target-arm/translate.c
parentb26eefb68e7942eeb689c81fd20e67e57ad95cd2 (diff)
downloadhqemu-f51bbbfefe73120a85a8d24a029d37c9c0f3a001.zip
hqemu-f51bbbfefe73120a85a8d24a029d37c9c0f3a001.tar.gz
ARM TCG conversion 2/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4139 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r--target-arm/translate.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index ef529eb..8669e94 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -205,6 +205,9 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
#define gen_sxtb16(var) tcg_gen_helper_1_1(HELPER_ADDR(sxtb16), var, var)
#define gen_uxtb16(var) tcg_gen_helper_1_1(HELPER_ADDR(uxtb16), var, var)
+#define gen_op_clz_T0(var) \
+ tcg_gen_helper_1_1(HELPER_ADDR(clz), cpu_T[0], cpu_T[0])
+
/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
tmp = (t0 ^ t1) & 0x8000;
t0 &= ~0x8000;
OpenPOWER on IntegriCloud