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| author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-08-01 02:31:54 +0000 |
|---|---|---|
| committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-08-01 02:31:54 +0000 |
| commit | 2e23213f26fc747b3a4de3c87906bfd3399e95fa (patch) | |
| tree | 50636c61a33c5c1ff0ff53a674ae2515116d7d31 /target-arm/translate.c | |
| parent | 0e7b8a9f0147e6833244331935e2ff895f96a8f8 (diff) | |
| download | hqemu-2e23213f26fc747b3a4de3c87906bfd3399e95fa.zip hqemu-2e23213f26fc747b3a4de3c87906bfd3399e95fa.tar.gz | |
Special-case iWMMXt register transfer insns, which are in ARM LDC2/STC2 class.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3107 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 3ce93f8..799aef2 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2230,6 +2230,13 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) gen_op_movl_T0_im(val); gen_bx(s); return; + } else if ((insn & 0x0e000f00) == 0x0c000100) { + if (arm_feature(env, ARM_FEATURE_IWMMXT)) { + /* iWMMXt register transfer. */ + if (env->cp15.c15_cpar & (1 << 1)) + if (!disas_iwmmxt_insn(env, s, insn)) + return; + } } else if ((insn & 0x0fe00000) == 0x0c400000) { /* Coprocessor double register transfer. */ } else if ((insn & 0x0f000010) == 0x0e000010) { |
