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author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-05-22 23:06:04 +0000 |
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committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-05-22 23:06:04 +0000 |
commit | 159f36638898f4ea671b7f56707dc6f1ec9681d4 (patch) | |
tree | 18db33b55721009468657df3ae2e88b08955a398 /target-arm/translate.c | |
parent | ba9a74dae0bb696ceab1ee2291cee43ef241a639 (diff) | |
download | hqemu-159f36638898f4ea671b7f56707dc6f1ec9681d4.zip hqemu-159f36638898f4ea671b7f56707dc6f1ec9681d4.tar.gz |
ARM undefined instruction execution (Jason Wessel)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1938 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r-- | target-arm/translate.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index e6e8c68..c582d4b 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -1589,6 +1589,15 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) case 0x5: case 0x6: case 0x7: + /* Check for undefined extension instructions + * per the ARM Bible IE: + * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx + */ + sh = (0xf << 20) | (0xf << 4); + if (op1 == 0x7 && ((insn & sh) == sh)) + { + goto illegal_op; + } /* load/store byte/word */ rn = (insn >> 16) & 0xf; rd = (insn >> 12) & 0xf; |