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author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-07 14:03:27 +0000 |
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committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-07 14:03:27 +0000 |
commit | ded9d29547922ba1ade973d6031313411c98e214 (patch) | |
tree | d25fa88d232052869b3271b4ebced9bffa0833d4 /target-arm/translate.c | |
parent | 662bbadd3529564e5bc4f1e5474979ac34872f0f (diff) | |
download | hqemu-ded9d29547922ba1ade973d6031313411c98e214.zip hqemu-ded9d29547922ba1ade973d6031313411c98e214.tar.gz |
ARM: fix usad8 and usada8 usage of registers (Mans Rullgard).
This fixes the destination and accumulator registers for the usad8
and usada8 instructions.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5912 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r-- | target-arm/translate.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 94528be..29ec0ed 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6556,12 +6556,12 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) tmp2 = load_reg(s, rs); gen_helper_usad8(tmp, tmp, tmp2); dead_tmp(tmp2); - if (rn != 15) { - tmp2 = load_reg(s, rn); + if (rd != 15) { + tmp2 = load_reg(s, rd); tcg_gen_add_i32(tmp, tmp, tmp2); dead_tmp(tmp2); } - store_reg(s, rd, tmp); + store_reg(s, rn, tmp); break; case 0x20: case 0x24: case 0x28: case 0x2c: /* Bitfield insert/clear. */ |