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author | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-21 13:48:32 +0000 |
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committer | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-21 13:48:32 +0000 |
commit | 36aa55dcd9775a2164d831d3d3e2a16977995f14 (patch) | |
tree | 8cae41e48031febf5bfbc04d0c84c639f62ed2ab /target-arm/translate.c | |
parent | 436d124b7d538b1fd9cf72edf17770664c309856 (diff) | |
download | hqemu-36aa55dcd9775a2164d831d3d3e2a16977995f14.zip hqemu-36aa55dcd9775a2164d831d3d3e2a16977995f14.tar.gz |
Add concat_i32_i64 op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r-- | target-arm/translate.c | 35 |
1 files changed, 13 insertions, 22 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 836b356..5d71349 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -1447,10 +1447,7 @@ static void gen_iwmmxt_movl_T0_T1_wRn(int rn) static void gen_iwmmxt_movl_wRn_T0_T1(int rn) { - tcg_gen_extu_i32_i64(cpu_V0, cpu_T[0]); - tcg_gen_extu_i32_i64(cpu_V1, cpu_T[0]); - tcg_gen_shli_i64(cpu_V1, cpu_V1, 32); - tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); + tcg_gen_concat_i32_i64(cpu_V0, cpu_T[0], cpu_T[1]); iwmmxt_store_reg(cpu_V0, rn); } @@ -4663,14 +4660,11 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) } else { tmp = neon_load_reg(rm + pass, 0); gen_neon_shift_narrow(size, tmp, tmp2, q, u); - tcg_gen_extu_i32_i64(cpu_V0, tmp); + tmp3 = neon_load_reg(rm + pass, 1); + gen_neon_shift_narrow(size, tmp3, tmp2, q, u); + tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3); dead_tmp(tmp); - tmp = neon_load_reg(rm + pass, 1); - gen_neon_shift_narrow(size, tmp, tmp2, q, u); - tcg_gen_extu_i32_i64(cpu_V1, tmp); - dead_tmp(tmp); - tcg_gen_shli_i64(cpu_V1, cpu_V1, 32); - tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); + dead_tmp(tmp3); } tmp = new_tmp(); if (op == 8 && !u) { @@ -5600,7 +5594,7 @@ static void gen_addq_lo(DisasContext *s, TCGv val, int rlow) TCGv tmp; TCGv tmp2; - /* Load 64-bit value rd:rn. */ + /* Load value and extend to 64 bits. */ tmp = tcg_temp_new(TCG_TYPE_I64); tmp2 = load_reg(s, rlow); tcg_gen_extu_i32_i64(tmp, tmp2); @@ -5612,19 +5606,16 @@ static void gen_addq_lo(DisasContext *s, TCGv val, int rlow) static void gen_addq(DisasContext *s, TCGv val, int rlow, int rhigh) { TCGv tmp; - TCGv tmp2; + TCGv tmpl; + TCGv tmph; /* Load 64-bit value rd:rn. */ + tmpl = load_reg(s, rlow); + tmph = load_reg(s, rhigh); tmp = tcg_temp_new(TCG_TYPE_I64); - tmp2 = load_reg(s, rhigh); - tcg_gen_extu_i32_i64(tmp, tmp2); - dead_tmp(tmp2); - tcg_gen_shli_i64(tmp, tmp, 32); - tcg_gen_add_i64(val, val, tmp); - - tmp2 = load_reg(s, rlow); - tcg_gen_extu_i32_i64(tmp, tmp2); - dead_tmp(tmp2); + tcg_gen_concat_i32_i64(tmp, tmpl, tmph); + dead_tmp(tmpl); + dead_tmp(tmph); tcg_gen_add_i64(val, val, tmp); } |