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author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2015-06-19 14:17:44 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2015-06-19 14:17:44 +0100 |
commit | 6cb0b013a1fa421cdfb83257cd33f855cc90649a (patch) | |
tree | d7c505b89b116dd870147145cb094d4848d4c213 /target-arm/machine.c | |
parent | 3281af8114c6b8ead02f08b58e3c36895c1ea047 (diff) | |
download | hqemu-6cb0b013a1fa421cdfb83257cd33f855cc90649a.zip hqemu-6cb0b013a1fa421cdfb83257cd33f855cc90649a.tar.gz |
target-arm: Add registers for PMSAv7
Define the arm CP registers for PMSAv7 and their accessor functions.
RGNR serves as a shared index that indexes into arrays storing the
DRBAR, DRSR and DRACR registers. DRBAR and friends have to be VMSDd
separately from the CP interface using a new PMSA specific VMSD
subsection.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 172cf135fbd8f5cea413c00e71cc1c3cac704744.1434501320.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/machine.c')
-rw-r--r-- | target-arm/machine.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/target-arm/machine.c b/target-arm/machine.c index 36365a5..9eb51df 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -125,6 +125,39 @@ static const VMStateDescription vmstate_thumb2ee = { } }; +static bool pmsav7_needed(void *opaque) +{ + ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; + + return arm_feature(env, ARM_FEATURE_MPU) && + arm_feature(env, ARM_FEATURE_V7); +} + +static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) +{ + ARMCPU *cpu = opaque; + + return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion; +} + +static const VMStateDescription vmstate_pmsav7 = { + .name = "cpu/pmsav7", + .version_id = 1, + .minimum_version_id = 1, + .needed = pmsav7_needed, + .fields = (VMStateField[]) { + VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), + VMSTATE_END_OF_LIST() + } +}; + static int get_cpsr(QEMUFile *f, void *opaque, size_t size) { ARMCPU *cpu = opaque; @@ -291,6 +324,7 @@ const VMStateDescription vmstate_arm_cpu = { &vmstate_iwmmxt, &vmstate_m, &vmstate_thumb2ee, + &vmstate_pmsav7, NULL } }; |