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author | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 11:57:09 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 12:03:44 +0000 |
commit | e9aa6c21483bc50767132c305284cd5446001df7 (patch) | |
tree | 4b93bd19b56596eecadbb68e1a9ea442fdafd131 /target-arm/helper.c | |
parent | 2ceb98c0079a68078947c222111238c7c7ae89b5 (diff) | |
download | hqemu-e9aa6c21483bc50767132c305284cd5446001df7.zip hqemu-e9aa6c21483bc50767132c305284cd5446001df7.tar.gz |
target-arm: Convert debug registers to cp_reginfo
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the
cp_reginfo scheme.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/helper.c')
-rw-r--r-- | target-arm/helper.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index f7c9a3a..a750637 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -56,6 +56,27 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +static const ARMCPRegInfo cp_reginfo[] = { + /* DBGDIDR: just RAZ. In particular this means the "debug architecture + * version" bits will read as a reserved value, which should cause + * Linux to not try to use the debug hardware. + */ + { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo v7_cp_reginfo[] = { + /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped + * debug components + */ + { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "DBGDRAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -65,6 +86,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) return; } + define_arm_cp_regs(cpu, cp_reginfo); + if (arm_feature(env, ARM_FEATURE_V7)) { + define_arm_cp_regs(cpu, v7_cp_reginfo); + } } ARMCPU *cpu_arm_init(const char *cpu_model) |