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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2014-05-27 17:09:52 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-05-27 17:09:52 +0100
commit28c9457df08755ef7d98eb58b17e0e0898553b41 (patch)
tree6e12461d1ffe338fc977d9d022f2762583e4e3a9 /target-arm/cpu.h
parent1b1742386c82541d65a5068d9d5da42c3b4f61a5 (diff)
downloadhqemu-28c9457df08755ef7d98eb58b17e0e0898553b41.zip
hqemu-28c9457df08755ef7d98eb58b17e0e0898553b41.tar.gz
target-arm: Add SPSR entries for EL2/HYP and EL3/MON
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-12-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 60414ac..5919dfd 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -143,7 +143,7 @@ typedef struct CPUARMState {
uint32_t spsr;
/* Banked registers. */
- uint64_t banked_spsr[6];
+ uint64_t banked_spsr[8];
uint32_t banked_r13[6];
uint32_t banked_r14[6];
@@ -563,7 +563,9 @@ enum arm_cpu_mode {
ARM_CPU_MODE_FIQ = 0x11,
ARM_CPU_MODE_IRQ = 0x12,
ARM_CPU_MODE_SVC = 0x13,
+ ARM_CPU_MODE_MON = 0x16,
ARM_CPU_MODE_ABT = 0x17,
+ ARM_CPU_MODE_HYP = 0x1a,
ARM_CPU_MODE_UND = 0x1b,
ARM_CPU_MODE_SYS = 0x1f
};
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