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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-04-15 19:18:49 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:34:06 +0100 |
| commit | f318cec6adcb73c688d68b0874686a30c0f34a2e (patch) | |
| tree | fa722ad17c8c35c4fae6391bbd88f007c25e2b9b /target-arm/cpu.h | |
| parent | 377a44ec8f2fac5b7bef41d212dfbabf53c8c810 (diff) | |
| download | hqemu-f318cec6adcb73c688d68b0874686a30c0f34a2e.zip hqemu-f318cec6adcb73c688d68b0874686a30c0f34a2e.tar.gz | |
target-arm: Implement CBAR for Cortex-A57
The Cortex-A57, like most of the other ARM cores, has a CBAR
register which defines the base address of the per-CPU
peripherals. However it has a 64-bit view as well as a
32-bit view; expand the QOM reset-cbar property from UINT32
to UINT64 so this can be specified, and implement the
32-bit and 64-bit views of a 64-bit CBAR.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index bebb333..c83f249 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -630,6 +630,7 @@ enum arm_features { ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ ARM_FEATURE_CBAR, /* has cp15 CBAR */ ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ + ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ }; static inline int arm_feature(CPUARMState *env, int feature) |
