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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2014-05-27 17:09:51 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-05-27 17:09:51 +0100
commitd81c519c40a24a49c96522a0deb834cdde264d77 (patch)
tree5ad6b66c089d9dd4323ab39136fe296737fb2de2 /target-arm/cpu.h
parent6947f05978806a7066fcaeccd8c187d577677328 (diff)
downloadhqemu-d81c519c40a24a49c96522a0deb834cdde264d77.zip
hqemu-d81c519c40a24a49c96522a0deb834cdde264d77.tar.gz
target-arm: Make esr_el1 an array
No functional change. Prepares for future addtion of EL2 and 3 versions of this reg. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-8-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index fabfe9e..a3cf375 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -185,7 +185,7 @@ typedef struct CPUARMState {
uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
uint32_t ifsr_el2; /* Fault status registers. */
- uint64_t esr_el1;
+ uint64_t esr_el[2];
uint32_t c6_region[8]; /* MPU base/size registers. */
uint64_t far_el1; /* Fault address registers. */
uint64_t par_el1; /* Translation result. */
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