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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-08-19 18:56:26 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-08-19 19:02:03 +0100 |
| commit | 662cefb7753c1f04d960b443c60e7622c83144d3 (patch) | |
| tree | 2116183e3c60a028c2628fcb32e09ebd445b2fdf /target-arm/cpu.h | |
| parent | 4051e12c5df1c46b542b28ed43f1614a42245ecf (diff) | |
| download | hqemu-662cefb7753c1f04d960b443c60e7622c83144d3.zip hqemu-662cefb7753c1f04d960b443c60e7622c83144d3.tar.gz | |
target-arm: Correctly handle PSTATE.SS when taking exception to AArch32
When an exception is taken to AArch32, we must clear the PSTATE.SS
bit for the exception handler, and must also ensure that the SS bit
is not set in the value saved to SPSR_<mode>. Achieve both of these
aims by clearing the bit in uncached_cpsr before saving it to the SPSR.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-arm/cpu.h')
0 files changed, 0 insertions, 0 deletions
