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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-10-24 12:19:13 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-10-24 12:19:13 +0100 |
| commit | 37e6456ef539b2c4d1b9438f3df90eb032a9618f (patch) | |
| tree | d7bc890b4fb05b19f12223ba63bad55005565ee6 /target-arm/cpu.h | |
| parent | 394043384337d3e84fe92ecc83bd90b0dcd661d5 (diff) | |
| download | hqemu-37e6456ef539b2c4d1b9438f3df90eb032a9618f.zip hqemu-37e6456ef539b2c4d1b9438f3df90eb032a9618f.tar.gz | |
target-arm: Add support for A32 and T32 HVC and SMC insns
Add support for HVC and SMC instructions to the A32 and
T32 decoder. Using these for real exceptions to EL2 or EL3
is currently not supported (the do_interrupt routine does
not handle them) but we require the instruction support to
implement PSCI.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1412865028-17725-6-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/cpu.h')
0 files changed, 0 insertions, 0 deletions
