summaryrefslogtreecommitdiffstats
path: root/target-arm/cpu.h
diff options
context:
space:
mode:
authorbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2007-04-30 02:02:17 +0000
committerbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2007-04-30 02:02:17 +0000
commit18c9b56060e6d69e38d0d91ffb02d510d8ce1971 (patch)
tree9d47bc9c28811fa847a85f845fa62c8e418a435b /target-arm/cpu.h
parenta171fe394a82e3a2dad76e901959d859b1966541 (diff)
downloadhqemu-18c9b56060e6d69e38d0d91ffb02d510d8ce1971.zip
hqemu-18c9b56060e6d69e38d0d91ffb02d510d8ce1971.tar.gz
Implement iwMMXt instruction set for the PXA270 cpu.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2752 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 6e2ae90..7cb08eb 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -129,6 +129,14 @@ typedef struct CPUARMState {
float_status fp_status;
} vfp;
+ /* iwMMXt coprocessor state. */
+ struct {
+ uint64_t regs[16];
+ uint64_t val;
+
+ uint32_t cregs[16];
+ } iwmmxt;
+
#if defined(CONFIG_USER_ONLY)
/* For usermode syscall translation. */
int eabi;
@@ -218,10 +226,21 @@ enum arm_cpu_mode {
#define ARM_VFP_FPINST 9
#define ARM_VFP_FPINST2 10
+/* iwMMXt coprocessor control registers. */
+#define ARM_IWMMXT_wCID 0
+#define ARM_IWMMXT_wCon 1
+#define ARM_IWMMXT_wCSSF 2
+#define ARM_IWMMXT_wCASF 3
+#define ARM_IWMMXT_wCGR0 8
+#define ARM_IWMMXT_wCGR1 9
+#define ARM_IWMMXT_wCGR2 10
+#define ARM_IWMMXT_wCGR3 11
+
enum arm_features {
ARM_FEATURE_VFP,
ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
+ ARM_FEATURE_IWMMXT /* Intel iwMMXt extension. */
};
static inline int arm_feature(CPUARMState *env, int feature)
OpenPOWER on IntegriCloud