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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2014-06-09 15:43:23 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-06-09 16:06:11 +0100 |
| commit | f1ecb913d81199758383b8cbc15f4eb435b91753 (patch) | |
| tree | f89668491c992e0bce53847a868db7c6fdfa764d /target-arm/cpu.h | |
| parent | d615efac7c4dc0984de31791c5c7d6b06408aadb (diff) | |
| download | hqemu-f1ecb913d81199758383b8cbc15f4eb435b91753.zip hqemu-f1ecb913d81199758383b8cbc15f4eb435b91753.tar.gz | |
target-arm: add support for v8 SHA1 and SHA256 instructions
This adds support for the SHA1 and SHA256 instructions that are available
on some v8 implementations of Aarch32.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401386724-26529-2-git-send-email-peter.maydell@linaro.org
[PMM:
* rebase
* fix bad indent
* add a missing UNDEF check for Q!=1 in the 3-reg SHA1/SHA256 case
* use g_assert_not_reached()
* don't re-extract bit 6 for the 2-reg-misc encodings
* set the ELF HWCAP2 bits for the new features
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7d8332e..14d5f21 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -635,6 +635,8 @@ enum arm_features { ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ ARM_FEATURE_EL2, /* has EL2 Virtualization support */ ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ + ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ + ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ }; static inline int arm_feature(CPUARMState *env, int feature) |
