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author | Peter Maydell <peter.maydell@linaro.org> | 2014-03-10 14:56:28 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2014-03-10 14:56:28 +0000 |
commit | af5199347a874db2214bf818151bad71b856ff37 (patch) | |
tree | 4bea347b54aa797e26bf10d31d0462b4d7d86dd4 /qemu-log.c | |
parent | e9d818b8b1a7fadc6c92256b716f1bc21b8daabc (diff) | |
download | hqemu-af5199347a874db2214bf818151bad71b856ff37.zip hqemu-af5199347a874db2214bf818151bad71b856ff37.tar.gz |
target-arm: Fix incorrect setting of E bit in CPSR
Commit 4cc35614a moved the exception mask bits out of env->uncached_cpsr
and into env->daif. However the env->daif contents are AArch64 style
mask bits, which include not just the AArch32 AIF bits but also the
new D bit (masks debug exceptions). This means that when reconstructing
the AArch32 CPSR value we must not allow the D bit in env->daif to get
into the CPSR, because the corresponding bit in the CPSR is E, the
endianness bit.
This bug didn't affect execution under TCG because we don't implement
endianness-swapping and so simply ignored the E bit; however it meant
that kernel booting under KVM failed, because KVM does honour the E bit.
Reported-by: Alexey Ignatov <lexszero@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'qemu-log.c')
0 files changed, 0 insertions, 0 deletions