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| author | Paolo Bonzini <pbonzini@redhat.com> | 2013-03-05 15:04:36 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2014-05-13 13:22:29 +0200 |
| commit | 4700a316df7d2cdcd256dcd64a10cec643f4dfa1 (patch) | |
| tree | f51f9f50e9514558cc4d7cc9a166968596eabfbd /os-win32.c | |
| parent | 4a92a558f49cb0693e36bd6d4f9217f298045be2 (diff) | |
| download | hqemu-4700a316df7d2cdcd256dcd64a10cec643f4dfa1.zip hqemu-4700a316df7d2cdcd256dcd64a10cec643f4dfa1.tar.gz | |
pc: port 92 reset requires a low->high transition
The PIIX datasheet says that "before another INIT pulse can be
generated via [port 92h], [bit 0] must be written back to a
zero.
This bug is masked right now because a full reset will clear the
value of port 92h. But once we implement soft reset correctly,
the next attempt to enable the A20 line by setting bit 1 (and
leaving the others untouched) will cause another reset.
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'os-win32.c')
0 files changed, 0 insertions, 0 deletions
