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author | Andreas Färber <afaerber@suse.de> | 2012-12-23 00:39:34 +0100 |
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committer | Andreas Färber <afaerber@suse.de> | 2012-12-23 00:40:49 +0100 |
commit | 501a7ce7270955be151c442c27620fa7af2f3ce5 (patch) | |
tree | 0374e4d581a0246074d55712b81baf01f3c439b6 /include/qemu/atomic.h | |
parent | 62e0c095450f6a7eb37914991f3f7966aa4da7a1 (diff) | |
parent | 36f25d2537c40c6c47f4abee5d31a24863d1adf7 (diff) | |
download | hqemu-501a7ce7270955be151c442c27620fa7af2f3ce5.zip hqemu-501a7ce7270955be151c442c27620fa7af2f3ce5.tar.gz |
Merge branch 'master' of git://git.qemu.org/qemu into qom-cpu
Adapt header include paths.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'include/qemu/atomic.h')
-rw-r--r-- | include/qemu/atomic.h | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h new file mode 100644 index 0000000..96a194b --- /dev/null +++ b/include/qemu/atomic.h @@ -0,0 +1,67 @@ +#ifndef __QEMU_BARRIER_H +#define __QEMU_BARRIER_H 1 + +/* Compiler barrier */ +#define barrier() asm volatile("" ::: "memory") + +#if defined(__i386__) + +#include "qemu/compiler.h" /* QEMU_GNUC_PREREQ */ + +/* + * Because of the strongly ordered x86 storage model, wmb() and rmb() are nops + * on x86(well, a compiler barrier only). Well, at least as long as + * qemu doesn't do accesses to write-combining memory or non-temporal + * load/stores from C code. + */ +#define smp_wmb() barrier() +#define smp_rmb() barrier() +/* + * We use GCC builtin if it's available, as that can use + * mfence on 32 bit as well, e.g. if built with -march=pentium-m. + * However, on i386, there seem to be known bugs as recently as 4.3. + * */ +#if QEMU_GNUC_PREREQ(4, 4) +#define smp_mb() __sync_synchronize() +#else +#define smp_mb() asm volatile("lock; addl $0,0(%%esp) " ::: "memory") +#endif + +#elif defined(__x86_64__) + +#define smp_wmb() barrier() +#define smp_rmb() barrier() +#define smp_mb() asm volatile("mfence" ::: "memory") + +#elif defined(_ARCH_PPC) + +/* + * We use an eieio() for wmb() on powerpc. This assumes we don't + * need to order cacheable and non-cacheable stores with respect to + * each other + */ +#define smp_wmb() asm volatile("eieio" ::: "memory") + +#if defined(__powerpc64__) +#define smp_rmb() asm volatile("lwsync" ::: "memory") +#else +#define smp_rmb() asm volatile("sync" ::: "memory") +#endif + +#define smp_mb() asm volatile("sync" ::: "memory") + +#else + +/* + * For (host) platforms we don't have explicit barrier definitions + * for, we use the gcc __sync_synchronize() primitive to generate a + * full barrier. This should be safe on all platforms, though it may + * be overkill for wmb() and rmb(). + */ +#define smp_wmb() __sync_synchronize() +#define smp_mb() __sync_synchronize() +#define smp_rmb() __sync_synchronize() + +#endif + +#endif |