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author | Peter Maydell <peter.maydell@linaro.org> | 2015-05-18 20:23:16 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2015-05-18 20:23:16 +0100 |
commit | 62bf3df432d93fa6eb0f355c460d6d784b7cbc1a (patch) | |
tree | 1130e9024e95c5479bca9ca0fd45557978daa82d /include/hw/char/cadence_uart.h | |
parent | 385057cbec9b4a0eb6150330c572e875ed714965 (diff) | |
parent | 18084b2f71b22b3ec3bf4828b8cb83d1d39e8502 (diff) | |
download | hqemu-62bf3df432d93fa6eb0f355c460d6d784b7cbc1a.zip hqemu-62bf3df432d93fa6eb0f355c460d6d784b7cbc1a.tar.gz |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150518-3' into staging
target-arm:
* New board model: xlnx-ep108
* Some more preparation for AArch64 EL2/EL3
* Fix bugs in access checking for generic counter registers
* Remove a stray '+' sign
# gpg: Signature made Mon May 18 20:13:05 2015 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
* remotes/pmaydell/tags/pull-target-arm-20150518-3: (21 commits)
target-arm: Remove unneeded '+'
target-arm: Correct accessfn for CNTV_TVAL_EL0
target-arm: Correct accessfn for CNTP_{CT}VAL_EL0
target-arm: Add WFx syndrome function
target-arm: Add EL3 and EL2 TCR checking
target-arm: Add TTBR regime function and use
linux-user/arm: Correct TARGET_NR_timerfd to TARGET_NR_timerfd_create
arm: xlnx-ep108: Add bootloading
arm: xlnx-ep108: Add external RAM
arm: Add xlnx-ep108 machine
arm: xlnx-zynqmp: Add UART support
char: cadence_uart: Split state struct and type into header
char: cadence_uart: Clean up variable names
arm: xlnx-zynqmp: Add GEM support
net: cadence_gem: Split state struct and type into header
net: cadence_gem: Clean up variable names
arm: xlnx-zynqmp: Connect CPU Timers to GIC
arm: xlnx-zynqmp: Add GIC
arm: Introduce Xilinx ZynqMP SoC
target-arm: cpu64: Add support for Cortex-A53
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/char/cadence_uart.h')
-rw-r--r-- | include/hw/char/cadence_uart.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h new file mode 100644 index 0000000..6310f52 --- /dev/null +++ b/include/hw/char/cadence_uart.h @@ -0,0 +1,53 @@ +/* + * Device model for Cadence UART + * + * Copyright (c) 2010 Xilinx Inc. + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) + * Copyright (c) 2012 PetaLogix Pty Ltd. + * Written by Haibing Ma + * M.Habib + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef CADENCE_UART_H + +#include "hw/sysbus.h" +#include "sysemu/char.h" +#include "qemu/timer.h" + +#define CADENCE_UART_RX_FIFO_SIZE 16 +#define CADENCE_UART_TX_FIFO_SIZE 16 + +#define CADENCE_UART_R_MAX (0x48/4) + +#define TYPE_CADENCE_UART "cadence_uart" +#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \ + TYPE_CADENCE_UART) + +typedef struct { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + uint32_t r[CADENCE_UART_R_MAX]; + uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE]; + uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE]; + uint32_t rx_wpos; + uint32_t rx_count; + uint32_t tx_count; + uint64_t char_tx_time; + CharDriverState *chr; + qemu_irq irq; + QEMUTimer *fifo_trigger_handle; +} CadenceUARTState; + +#define CADENCE_UART_H +#endif |