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authorPeter Maydell <peter.maydell@linaro.org>2014-09-11 10:36:50 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-09-11 10:36:50 +0100
commitfc3b9aa876901ab2317923ce1ab09043eee7f2a4 (patch)
treeb18935b9a01126bbe07fe1b5e91cce888e65fff0 /hw
parent10601bef566461efbea81ee344ed3355ce71954a (diff)
parente6043e92c2812a56b8f6cf35d5512067c746ce21 (diff)
downloadhqemu-fc3b9aa876901ab2317923ce1ab09043eee7f2a4.zip
hqemu-fc3b9aa876901ab2317923ce1ab09043eee7f2a4.tar.gz
Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-20140910-1' into staging
xhci PCIe endpoint migration compatibility fix # gpg: Signature made Wed 10 Sep 2014 06:35:20 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-usb-20140910-1: xhci PCIe endpoint migration compatibility fix Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/usb/hcd-xhci.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index bbe4c5f..73ced1f 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -499,6 +499,7 @@ enum xhci_flags {
XHCI_FLAG_USE_MSI = 1,
XHCI_FLAG_USE_MSI_X,
XHCI_FLAG_SS_FIRST,
+ XHCI_FLAG_FORCE_PCIE_ENDCAP,
};
static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
@@ -3626,7 +3627,8 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
&xhci->mem);
- if (pci_bus_is_express(dev->bus)) {
+ if (pci_bus_is_express(dev->bus) ||
+ xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
ret = pcie_endpoint_cap_init(dev, 0xa0);
assert(ret >= 0);
}
@@ -3855,6 +3857,8 @@ static Property xhci_properties[] = {
DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true),
DEFINE_PROP_BIT("superspeed-ports-first",
XHCIState, flags, XHCI_FLAG_SS_FIRST, true),
+ DEFINE_PROP_BIT("force-pcie-endcap", XHCIState, flags,
+ XHCI_FLAG_FORCE_PCIE_ENDCAP, false),
DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS),
DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS),
DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
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