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authoraliguori <aliguori@c046a42c-6fe2-441c-8c8c-71466251a162>2009-02-11 15:21:41 +0000
committeraliguori <aliguori@c046a42c-6fe2-441c-8c8c-71466251a162>2009-02-11 15:21:41 +0000
commitca2c72be18dd8104fa9108ecefcd562e85672360 (patch)
treed7652e8057de2c9010bbbdde918bdb8b79cb8527 /hw
parent5e3cb5347e9b650bdf8015da3c310b2669219294 (diff)
downloadhqemu-ca2c72be18dd8104fa9108ecefcd562e85672360.zip
hqemu-ca2c72be18dd8104fa9108ecefcd562e85672360.tar.gz
qemu: pci hotplug GPE support (Marcelo Tosatti)
Enable the corresponding bit on the PCIST region and trigger the SCI and handle the _EJ0 notifications. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6608 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw')
-rw-r--r--hw/acpi.c94
1 files changed, 94 insertions, 0 deletions
diff --git a/hw/acpi.c b/hw/acpi.c
index a6284bf..0702017 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -563,13 +563,21 @@ void qemu_system_powerdown(void)
#endif
#define GPE_BASE 0xafe0
+#define PCI_BASE 0xae00
+#define PCI_EJ_BASE 0xae08
struct gpe_regs {
uint16_t sts; /* status */
uint16_t en; /* enabled */
};
+struct pci_status {
+ uint32_t up;
+ uint32_t down;
+};
+
static struct gpe_regs gpe;
+static struct pci_status pci0_status;
static uint32_t gpe_readb(void *opaque, uint32_t addr)
{
@@ -623,9 +631,95 @@ static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
#endif
}
+static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
+{
+ uint32_t val = 0;
+ struct pci_status *g = opaque;
+ switch (addr) {
+ case PCI_BASE:
+ val = g->up;
+ break;
+ case PCI_BASE + 4:
+ val = g->down;
+ break;
+ default:
+ break;
+ }
+
+#if defined(DEBUG)
+ printf("pcihotplug read %lx == %lx\n", addr, val);
+#endif
+ return val;
+}
+
+static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ struct pci_status *g = opaque;
+ switch (addr) {
+ case PCI_BASE:
+ g->up = val;
+ break;
+ case PCI_BASE + 4:
+ g->down = val;
+ break;
+ }
+
+#if defined(DEBUG)
+ printf("pcihotplug write %lx <== %d\n", addr, val);
+#endif
+}
+
+static uint32_t pciej_read(void *opaque, uint32_t addr)
+{
+#if defined(DEBUG)
+ printf("pciej read %lx == %lx\n", addr, val);
+#endif
+ return 0;
+}
+
+static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ int slot = ffs(val) - 1;
+
+#if defined(DEBUG)
+ printf("pciej write %lx <== %d\n", addr, val);
+#endif
+}
+
void qemu_system_hot_add_init(void)
{
register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
register_ioport_read(GPE_BASE, 4, 1, gpe_readb, &gpe);
+ register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
+ register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, &pci0_status);
+
+ register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL);
+ register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, NULL);
+}
+
+static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
+{
+ g->sts |= 2;
+ g->en |= 2;
+ p->up |= (1 << slot);
+}
+
+static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
+{
+ g->sts |= 2;
+ g->en |= 2;
+ p->down |= (1 << slot);
+}
+
+void qemu_system_device_hot_add(int bus, int slot, int state)
+{
+ qemu_set_irq(pm_state->irq, 1);
+ pci0_status.up = 0;
+ pci0_status.down = 0;
+ if (state)
+ enable_device(&pci0_status, &gpe, slot);
+ else
+ disable_device(&pci0_status, &gpe, slot);
+ qemu_set_irq(pm_state->irq, 0);
}
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