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authorNadav Amit <namit@cs.technion.ac.il>2015-04-13 02:32:08 +0300
committerPaolo Bonzini <pbonzini@redhat.com>2015-04-28 22:14:14 +0200
commitb8eb5512fd8a115f164edbbe897cdf8884920ccb (patch)
tree0681044607c2feb1ec1d1dc4527b8bf911363090 /hw
parent7398dfc7799a50097803db4796c7edb6cd7d47a1 (diff)
downloadhqemu-b8eb5512fd8a115f164edbbe897cdf8884920ccb.zip
hqemu-b8eb5512fd8a115f164edbbe897cdf8884920ccb.tar.gz
target-i386: disable LINT0 after reset
Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long gone and therefore this hack is no longer needed. Since it violates the specifications, it is removed. Signed-off-by: Nadav Amit <namit@cs.technion.ac.il> Message-Id: <1428881529-29459-2-git-send-email-namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/intc/apic_common.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
index 042e960..d38d24b 100644
--- a/hw/intc/apic_common.c
+++ b/hw/intc/apic_common.c
@@ -243,15 +243,6 @@ static void apic_reset_common(DeviceState *dev)
info->vapic_base_update(s);
apic_init_reset(dev);
-
- if (bsp) {
- /*
- * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
- * time typically by BIOS, so PIC interrupt can be delivered to the
- * processor when local APIC is enabled.
- */
- s->lvt[APIC_LVT_LINT0] = 0x700;
- }
}
/* This function is only used for old state version 1 and 2 */
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