diff options
author | Alexander Graf <agraf@suse.de> | 2009-12-21 14:02:39 +0100 |
---|---|---|
committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-12-21 16:03:03 +0100 |
commit | 73b01960b4af0e75c955757034a91b6370a4edb8 (patch) | |
tree | c18182f35a0b9b787c26ac5f596c844011916b27 /hw | |
parent | b711de9565d3c8f758956dfa96b648cc321577b6 (diff) | |
download | hqemu-73b01960b4af0e75c955757034a91b6370a4edb8.zip hqemu-73b01960b4af0e75c955757034a91b6370a4edb8.tar.gz |
PPC: Make DCR uint32_t
For what I know DCR is always 32 bits wide, so we should also use uint32_t to
pass it along the stacks.
This fixes a warning when compiling qemu-system-ppc64 with KVM enabled, making
it compile without --disable-werror
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/ppc.c | 4 | ||||
-rw-r--r-- | hw/ppc.h | 4 | ||||
-rw-r--r-- | hw/ppc405_uc.c | 46 | ||||
-rw-r--r-- | hw/ppc4xx_devs.c | 14 |
4 files changed, 34 insertions, 34 deletions
@@ -1009,7 +1009,7 @@ struct ppc_dcr_t { int (*write_error)(int dcrn); }; -int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) +int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) { ppc_dcrn_t *dcr; @@ -1029,7 +1029,7 @@ int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) return -1; } -int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) +int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) { ppc_dcrn_t *dcr; @@ -13,8 +13,8 @@ static inline void clk_setup (clk_setup_t *clk, uint32_t freq) clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq); /* Embedded PowerPC DCR management */ -typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn); -typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val); +typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn); +typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val); int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn), int (*dcr_write_error)(int dcrn)); int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index 052f902..bfcb791 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -107,10 +107,10 @@ struct ppc4xx_plb_t { uint32_t besr; }; -static target_ulong dcr_read_plb (void *opaque, int dcrn) +static uint32_t dcr_read_plb (void *opaque, int dcrn) { ppc4xx_plb_t *plb; - target_ulong ret; + uint32_t ret; plb = opaque; switch (dcrn) { @@ -132,7 +132,7 @@ static target_ulong dcr_read_plb (void *opaque, int dcrn) return ret; } -static void dcr_write_plb (void *opaque, int dcrn, target_ulong val) +static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) { ppc4xx_plb_t *plb; @@ -189,10 +189,10 @@ struct ppc4xx_pob_t { uint32_t besr[2]; }; -static target_ulong dcr_read_pob (void *opaque, int dcrn) +static uint32_t dcr_read_pob (void *opaque, int dcrn) { ppc4xx_pob_t *pob; - target_ulong ret; + uint32_t ret; pob = opaque; switch (dcrn) { @@ -212,7 +212,7 @@ static target_ulong dcr_read_pob (void *opaque, int dcrn) return ret; } -static void dcr_write_pob (void *opaque, int dcrn, target_ulong val) +static void dcr_write_pob (void *opaque, int dcrn, uint32_t val) { ppc4xx_pob_t *pob; @@ -410,10 +410,10 @@ enum { EBC0_CFGDATA = 0x013, }; -static target_ulong dcr_read_ebc (void *opaque, int dcrn) +static uint32_t dcr_read_ebc (void *opaque, int dcrn) { ppc4xx_ebc_t *ebc; - target_ulong ret; + uint32_t ret; ebc = opaque; switch (dcrn) { @@ -494,7 +494,7 @@ static target_ulong dcr_read_ebc (void *opaque, int dcrn) return ret; } -static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val) +static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val) { ppc4xx_ebc_t *ebc; @@ -627,7 +627,7 @@ struct ppc405_dma_t { uint32_t pol; }; -static target_ulong dcr_read_dma (void *opaque, int dcrn) +static uint32_t dcr_read_dma (void *opaque, int dcrn) { ppc405_dma_t *dma; @@ -636,7 +636,7 @@ static target_ulong dcr_read_dma (void *opaque, int dcrn) return 0; } -static void dcr_write_dma (void *opaque, int dcrn, target_ulong val) +static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) { ppc405_dma_t *dma; @@ -914,10 +914,10 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, } } -static target_ulong dcr_read_ocm (void *opaque, int dcrn) +static uint32_t dcr_read_ocm (void *opaque, int dcrn) { ppc405_ocm_t *ocm; - target_ulong ret; + uint32_t ret; ocm = opaque; switch (dcrn) { @@ -941,7 +941,7 @@ static target_ulong dcr_read_ocm (void *opaque, int dcrn) return ret; } -static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val) +static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val) { ppc405_ocm_t *ocm; uint32_t isarc, dsarc, isacntl, dsacntl; @@ -1578,10 +1578,10 @@ struct ppc40x_mal_t { static void ppc40x_mal_reset (void *opaque); -static target_ulong dcr_read_mal (void *opaque, int dcrn) +static uint32_t dcr_read_mal (void *opaque, int dcrn) { ppc40x_mal_t *mal; - target_ulong ret; + uint32_t ret; mal = opaque; switch (dcrn) { @@ -1650,7 +1650,7 @@ static target_ulong dcr_read_mal (void *opaque, int dcrn) return ret; } -static void dcr_write_mal (void *opaque, int dcrn, target_ulong val) +static void dcr_write_mal (void *opaque, int dcrn, uint32_t val) { ppc40x_mal_t *mal; int idx; @@ -1951,10 +1951,10 @@ static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); } -static target_ulong dcr_read_crcpc (void *opaque, int dcrn) +static uint32_t dcr_read_crcpc (void *opaque, int dcrn) { ppc405cr_cpc_t *cpc; - target_ulong ret; + uint32_t ret; cpc = opaque; switch (dcrn) { @@ -1991,7 +1991,7 @@ static target_ulong dcr_read_crcpc (void *opaque, int dcrn) return ret; } -static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val) +static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val) { ppc405cr_cpc_t *cpc; @@ -2353,10 +2353,10 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); } -static target_ulong dcr_read_epcpc (void *opaque, int dcrn) +static uint32_t dcr_read_epcpc (void *opaque, int dcrn) { ppc405ep_cpc_t *cpc; - target_ulong ret; + uint32_t ret; cpc = opaque; switch (dcrn) { @@ -2393,7 +2393,7 @@ static target_ulong dcr_read_epcpc (void *opaque, int dcrn) return ret; } -static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val) +static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val) { ppc405ep_cpc_t *cpc; diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c index 7921ebf..37a3948 100644 --- a/hw/ppc4xx_devs.c +++ b/hw/ppc4xx_devs.c @@ -183,10 +183,10 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level) ppcuic_trigger_irq(uic); } -static target_ulong dcr_read_uic (void *opaque, int dcrn) +static uint32_t dcr_read_uic (void *opaque, int dcrn) { ppcuic_t *uic; - target_ulong ret; + uint32_t ret; uic = opaque; dcrn -= uic->dcr_base; @@ -229,13 +229,13 @@ static target_ulong dcr_read_uic (void *opaque, int dcrn) return ret; } -static void dcr_write_uic (void *opaque, int dcrn, target_ulong val) +static void dcr_write_uic (void *opaque, int dcrn, uint32_t val) { ppcuic_t *uic; uic = opaque; dcrn -= uic->dcr_base; - LOG_UIC("%s: dcr %d val " TARGET_FMT_lx "\n", __func__, dcrn, val); + LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val); switch (dcrn) { case DCR_UICSR: uic->uicsr &= ~val; @@ -448,10 +448,10 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) } } -static target_ulong dcr_read_sdram (void *opaque, int dcrn) +static uint32_t dcr_read_sdram (void *opaque, int dcrn) { ppc4xx_sdram_t *sdram; - target_ulong ret; + uint32_t ret; sdram = opaque; switch (dcrn) { @@ -516,7 +516,7 @@ static target_ulong dcr_read_sdram (void *opaque, int dcrn) return ret; } -static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val) +static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) { ppc4xx_sdram_t *sdram; |