diff options
author | Paul Brook <paul@codesourcery.com> | 2009-11-13 03:30:33 +0000 |
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committer | Paul Brook <paul@codesourcery.com> | 2009-11-13 04:04:18 +0000 |
commit | 26e92f65525ef4446a500d85e185cf78835922aa (patch) | |
tree | 4297dd3341245566647126edbd5fee80a5ef24af /hw | |
parent | dbe73d7f3b85b9c1473d1400bc29ff495d8c1322 (diff) | |
download | hqemu-26e92f65525ef4446a500d85e185cf78835922aa.zip hqemu-26e92f65525ef4446a500d85e185cf78835922aa.tar.gz |
Realview/EB procid hacks
Guess core tile ID based on CPU type.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/arm_sysctl.c | 8 | ||||
-rw-r--r-- | hw/primecell.h | 2 | ||||
-rw-r--r-- | hw/realview.c | 12 | ||||
-rw-r--r-- | hw/versatilepb.c | 2 |
4 files changed, 18 insertions, 6 deletions
diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c index 856e770..0cb2ffc 100644 --- a/hw/arm_sysctl.c +++ b/hw/arm_sysctl.c @@ -25,6 +25,7 @@ typedef struct { uint32_t flags; uint32_t nvflags; uint32_t resetlevel; + uint32_t proc_id; } arm_sysctl_state; static void arm_sysctl_reset(DeviceState *d) @@ -89,8 +90,7 @@ static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset) case 0x60: /* MISC */ return 0; case 0x84: /* PROCID0 */ - /* ??? Don't know what the proper value for the core tile ID is. */ - return 0x02000000; + return s->proc_id; case 0x88: /* PROCID1 */ return 0xff000000; case 0x64: /* DMAPSR0 */ @@ -215,13 +215,14 @@ static int arm_sysctl_init1(SysBusDevice *dev) } /* Legacy helper function. */ -void arm_sysctl_init(uint32_t base, uint32_t sys_id) +void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id) { DeviceState *dev; dev = qdev_create(NULL, "realview_sysctl"); qdev_prop_set_uint32(dev, "sys_id", sys_id); qdev_init_nofail(dev); + qdev_prop_set_uint32(dev, "proc_id", proc_id); sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); } @@ -232,6 +233,7 @@ static SysBusDeviceInfo arm_sysctl_info = { .qdev.reset = arm_sysctl_reset, .qdev.props = (Property[]) { DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0), + DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0), DEFINE_PROP_END_OF_LIST(), } }; diff --git a/hw/primecell.h b/hw/primecell.h index 490ef8c..fb456ad 100644 --- a/hw/primecell.h +++ b/hw/primecell.h @@ -9,6 +9,6 @@ void *pl080_init(uint32_t base, qemu_irq irq, int nchannels); /* arm_sysctl.c */ -void arm_sysctl_init(uint32_t base, uint32_t sys_id); +void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id); #endif diff --git a/hw/realview.c b/hw/realview.c index 95ad727..a14c8a0 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -51,6 +51,7 @@ static void realview_init(ram_addr_t ram_size, int done_smc = 0; qemu_irq cpu_irq[4]; int ncpu; + uint32_t proc_id = 0; if (!cpu_model) cpu_model = "arm926"; @@ -73,13 +74,22 @@ static void realview_init(ram_addr_t ram_size, qemu_register_reset(secondary_cpu_reset, env); } } + if (arm_feature(env, ARM_FEATURE_V7)) { + proc_id = 0x0e000000; + } else if (arm_feature(env, ARM_FEATURE_V6K)) { + proc_id = 0x06000000; + } else if (arm_feature(env, ARM_FEATURE_V6)) { + proc_id = 0x04000000; + } else { + proc_id = 0x02000000; + } ram_offset = qemu_ram_alloc(ram_size); /* ??? RAM should repeat to fill physical memory space. */ /* SDRAM at address zero. */ cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); - arm_sysctl_init(0x10000000, 0xc1400400); + arm_sysctl_init(0x10000000, 0xc1400400, proc_id); if (ncpu == 1) { /* ??? The documentation says GIC1 is nFIQ and either GIC2 or GIC3 diff --git a/hw/versatilepb.c b/hw/versatilepb.c index e8ebdf1..226c616 100644 --- a/hw/versatilepb.c +++ b/hw/versatilepb.c @@ -184,7 +184,7 @@ static void versatile_init(ram_addr_t ram_size, /* SDRAM at address zero. */ cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); - arm_sysctl_init(0x10000000, 0x41007004); + arm_sysctl_init(0x10000000, 0x41007004, 0x02000000); cpu_pic = arm_pic_init_cpu(env); dev = sysbus_create_varargs("pl190", 0x10140000, cpu_pic[0], cpu_pic[1], NULL); |