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| author | Jan Beulich <jbeulich@suse.com> | 2015-06-02 15:07:01 +0000 |
|---|---|---|
| committer | Stefano Stabellini <stefano.stabellini@eu.citrix.com> | 2015-06-02 15:07:01 +0000 |
| commit | 0ad3393ad032f76e88b4dbd04d36ad84dff75dd6 (patch) | |
| tree | 08b672c79409f158f54a1c3e9dcf75d54b5ece82 /hw/xen | |
| parent | 45ebe3916ab16f859ed930e92fbd52d84d5dcdaf (diff) | |
| download | hqemu-0ad3393ad032f76e88b4dbd04d36ad84dff75dd6.zip hqemu-0ad3393ad032f76e88b4dbd04d36ad84dff75dd6.tar.gz | |
xen/pt: mark reserved bits in PCI config space fields
The adjustments are solely to make the subsequent patches work right
(and hence make the patch set consistent), namely if permissive mode
(introduced by the last patch) gets used (as both reserved registers
and reserved fields must be similarly protected from guest access in
default mode, but the guest should be allowed access to them in
permissive mode).
This is a preparatory patch for XSA-131.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Diffstat (limited to 'hw/xen')
| -rw-r--r-- | hw/xen/xen_pt.h | 2 | ||||
| -rw-r--r-- | hw/xen/xen_pt_config_init.c | 14 |
2 files changed, 11 insertions, 5 deletions
diff --git a/hw/xen/xen_pt.h b/hw/xen/xen_pt.h index 8c9b6c2..f9795eb 100644 --- a/hw/xen/xen_pt.h +++ b/hw/xen/xen_pt.h @@ -101,6 +101,8 @@ struct XenPTRegInfo { uint32_t offset; uint32_t size; uint32_t init_val; + /* reg reserved field mask (ON:reserved, OFF:defined) */ + uint32_t res_mask; /* reg read only field mask (ON:RO/ROS, OFF:other) */ uint32_t ro_mask; /* reg emulate field mask (ON:emu, OFF:passthrough) */ diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c index 9f6c00e..efd8bac 100644 --- a/hw/xen/xen_pt_config_init.c +++ b/hw/xen/xen_pt_config_init.c @@ -578,7 +578,7 @@ static XenPTRegInfo xen_pt_emu_reg_header0[] = { .offset = PCI_COMMAND, .size = 2, .init_val = 0x0000, - .ro_mask = 0xF880, + .res_mask = 0xF880, .emu_mask = 0x0743, .init = xen_pt_common_reg_init, .u.w.read = xen_pt_word_reg_read, @@ -603,7 +603,8 @@ static XenPTRegInfo xen_pt_emu_reg_header0[] = { .offset = PCI_STATUS, .size = 2, .init_val = 0x0000, - .ro_mask = 0x06FF, + .res_mask = 0x0007, + .ro_mask = 0x06F8, .emu_mask = 0x0010, .init = xen_pt_status_reg_init, .u.w.read = xen_pt_word_reg_read, @@ -980,7 +981,8 @@ static XenPTRegInfo xen_pt_emu_reg_pm[] = { .offset = PCI_PM_CTRL, .size = 2, .init_val = 0x0008, - .ro_mask = 0xE1FC, + .res_mask = 0x00F0, + .ro_mask = 0xE10C, .emu_mask = 0x810B, .init = xen_pt_common_reg_init, .u.w.read = xen_pt_word_reg_read, @@ -1268,7 +1270,8 @@ static XenPTRegInfo xen_pt_emu_reg_msi[] = { .offset = PCI_MSI_FLAGS, .size = 2, .init_val = 0x0000, - .ro_mask = 0xFF8E, + .res_mask = 0xFE00, + .ro_mask = 0x018E, .emu_mask = 0x017E, .init = xen_pt_msgctrl_reg_init, .u.w.read = xen_pt_word_reg_read, @@ -1446,7 +1449,8 @@ static XenPTRegInfo xen_pt_emu_reg_msix[] = { .offset = PCI_MSI_FLAGS, .size = 2, .init_val = 0x0000, - .ro_mask = 0x3FFF, + .res_mask = 0x3800, + .ro_mask = 0x07FF, .emu_mask = 0x0000, .init = xen_pt_msixctrl_reg_init, .u.w.read = xen_pt_word_reg_read, |
