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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-02-07 15:18:14 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-02-07 15:18:14 +0000 |
| commit | c2432a42fe13c3c6774f5443ac8f6f7261fe91d1 (patch) | |
| tree | dc2546455f0f9f0751aca0e407ce7929996ce627 /hw/sh7750_regs.h | |
| parent | 68af3f249157f2538fea806622c45f537d65c9bc (diff) | |
| download | hqemu-c2432a42fe13c3c6774f5443ac8f6f7261fe91d1.zip hqemu-c2432a42fe13c3c6774f5443ac8f6f7261fe91d1.tar.gz | |
SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6548 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/sh7750_regs.h')
| -rw-r--r-- | hw/sh7750_regs.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/hw/sh7750_regs.h b/hw/sh7750_regs.h index c8fb328..5a23a2c 100644 --- a/hw/sh7750_regs.h +++ b/hw/sh7750_regs.h @@ -979,6 +979,17 @@ #define SH7750_RFCR_KEY 0xA400 /* RFCR write key */ +/* Synchronous DRAM mode registers - SDMR */ +#define SH7750_SDMR2_REGOFS 0x900000 /* base offset */ +#define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */ +#define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS) +#define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS) + +#define SH7750_SDMR3_REGOFS 0x940000 /* offset */ +#define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */ +#define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS) +#define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS) + /* * Direct Memory Access Controller (DMAC) */ @@ -1262,7 +1273,5 @@ */ #define SH7750_BCR3_A7 0x1f800050 #define SH7750_BCR4_A7 0x1e0a00f0 -#define SH7750_PRECHARGE0_A7 0x1f900088 -#define SH7750_PRECHARGE1_A7 0x1f940088 #endif |
